129results about How to "Delay problem" patented technology

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

The invention provides a method for assisting handover of a user terminal's, UT's, communication session in an integrated multi RAT network, said method to be carried out by an RNCI being installed in said network, said method comprising the following steps:— receiving a “Handover Candidate” message comprising a message type identifier information element identifying said message as being a “Handover Candidate” message and which message identifies said session and which message further identifies a candidate RNC of said network, wherein said candidate RNC constitutes an RNC handover candidate for said session,— establishing the identity of said RNC by investigating said message,— associating said communication session with said candidate RNC identified in the previous step. The invention provides an RNC1, RNC2, and software, realising the method according to the invention.

A device for generating composite images of dynamically changing surgical anatomy includes circuitry configured to receive, from an endoscopic imaging device, endoscopic image data. The circuitry is configured to receive, from a tomographic imaging device, intra-operative tomographic image data. The circuitry is configured to receive, from a tracking device, spatial tracking data corresponding to the endoscopic imaging device and the tomographic imaging device. The circuitry is configured to generate real-time dynamically changing composite image data by overlaying, based on the spatial tracking data, the intra-operative tomographic image data on the endoscopic image data. The circuitry is configured to output the composite image data to a display.

The invention provides a method for assisting handover of a communication session associated with a UT from a first radio access point, AP1, to a second radio access point, AP2, in a radio access network, said method to be carried out by said AP1 and comprising the steps of:—receiving a handover intention notify message comprising a session identifier identifying said session and indicating that said UT intends to perform a session handover,—assigning said session a buffer memory space in a memory of said AP1,—buffering downlink data packets addressed to said UT in said buffer memory as a response on receiving said handover intention notify message. The invention further provides a UT, an AP1, AP2, an AR, and software program / s co-operating and / or realizing the method according to the invention. The invention provides a smoother handover.

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

A liquid crystal display device includes a gate driving shift register having symmetrically split circuit portions by which each of plural gate lines is dually driven from both ends of the gate line during ripple-through scanning of rows of the LCD device. The LCD device includes a timing controller generating an output enable signal and a gate clock, where the timing controller adjusts a timing of a load signal for deciding a data output timing point when data will be loaded into a currently activated display row. The data output timing point is a function of a delay measuring feedback signal that is used to measure the cumulative delays of the sequentially connected stages of the shift register.

A user-centered interface agent eases the problem of unfamiliar user interfaces on host computers. The agent operates by learning user preferences and typical behaviors and predicting the user's preferred user interface for different types of host computers. Most of the agent's learning is through observation, requiring minimal-initialization by the user. The interface agent consists of a learning program which operates on the user's primary computer, a shadow program which is installed on a Personal Digital Assistant (PDA), and a remote program which operates on host computers. The role of the PDA includes the transfer of data between the primary and remote machines, and the PDA can also be the user's primary computer. On the primary computer, the agent learns a user's preference by observing the user's actions. The user may run agent-training module or directly query and modify the agent's current state of knowledge, but the user is not forced to explicitly teach the agent. The learning algorithm may be statistical, rule-based, case-based, neural network, or employ any other technique for reasoning under uncertainty. The automated way of reaching a usable configuration has a particular advantage for individuals with disabilities who require configuration before they can use a new computer system.

The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and / or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and an array for processing data comprising a plurality of data processing cells, e.g. a preferably coarse grain and / or preferably runtime reconfigurable data processor, FPGA, DFP, DSP, XPP or chaemeleon-technology-like data processing fabric, wherein the array is coupled to the instruction pipeline.

A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Load balanced transport of best efforts traffic together with delay-bounded traffic over a multilink bundle combines fragmentation and fragment distribution for best efforts packets with per-flow balancing for delay-bounded traffic. In the preferred embodiments, the best efforts packets receive Multilink Protocol treatment, including fragmentation and addition of sequence headers. Fragments of packets for one such communication go over the various links within the bundle, as appropriate for load balancing on the links. For each delay-bounded flow, such as for a VOIP service, the sending node hashes the packet header data and applies all packets for the flow to one of the links, assigned as a function of the hash value. Different flow headers produce different hash results; therefore the node sends different flows over the different links in a substantially balanced manner.

A protective garment configured to facilitate easy donning of the garment is described. The sleeves and legs are shorted and held in a donning configuration by releaseably affixing at least a portion of upper and lower segments of the interior surface of each limb. This allows the garment to be handled and donned by the wearer, without the wearer touching an exterior surface of the garment. A method of preparing a protective garment for donning and a method of donning such a garment is also disclosed.

A DC to DC converter receives a DC input voltage and generates an output DC voltage. A current sensor measures a DC input current. A control circuit is coupled to the current sensor for controlling the DC to DC converter to have a constant DC input current.

The present invention relates to an organic light emitting display device, a mother substrate, and a testing method, in which a sheet unit test is performed by directly supplying a test signal to a display region, rather than passing through a data distributor. The organic light emitting display device includes: a display region including pixels coupled to scan lines and data lines; a scan driver for supplying scan signals to the scan lines; a data driver for supplying data signals to output lines; a data distributor for supplying data signals to the data lines; a transistor group including transistors each coupled to one or more of the data lines; and a first wire group and a second wire group, wherein one of the wires included in the first wire group and the second wire group is coupled to gate electrodes of various transistors in the transistor group.

The present invention relates to a wireless communication method for simultaneous data communication and a wireless communication terminal using the same, and more particularly, to a wireless communication method for suppressing interference between terminals and ensuring fairness when performing data simultaneous communication for spatial reuse of communication system and wireless communication terminal using the same.For this, provided are a wireless communication method and a wireless communication terminal using the same. The method includes: receiving a wireless signal of a specific channel; extracting basic service set (BSS) identifier information of the received wireless signal; extracting length information from the wireless signal wherein the length information represents information relating to a transmission completion time point of the wireless signal; and adjusting a data transmission period of the terminal based on the extracted length information, when the BSS identifier information of the wireless signal is different from BSS identifier information of the terminal.

An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs.

The present invention provides a shift register unit, a gate driving circuit and a display device, which belongs to the field of display technology. The shift register unit of the present invention comprises: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module.

A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN / GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.

An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop, through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. A set of interconnected storage-shelf routers within a storage shelf can be accessed through a single port of an FC arbitrated loop or other high-bandwidth communications medium. Because, in one implementation, eight storage-shelf routers can be interconnected within a storage shelf to provide highly available interconnection of sixty-four disk drives within the storage shelf to an FC arbitrated loop via a single FC-arbitrated-loop port, a single FC arbitrated loop including a disk-array controller, may interconnect 8,000 individual disk drives to the disk-array controller within a disk array. The storage-shelf router can serve to translate FC-based communications protocols into one or more communication protocols appropriate to the internal links, providing for use of less expensive, non-FC-compatible disk drives within the storage shelf.

Communication network and a corresponding method are disclosed for operating the communication network that has a packet switched protocol based cellular telephone network comprising a first layer for transferring signalling information assigned to a telephone call being processed by the communication network, a second layer for transferring payload information assigned to the telephone call and an interface for coupling the cellular telephone network to a further network, the interface comprising a signalling information exchange function between the cellular telephone network and the further network and a payload information exchange function between the cellular telephone network and the further network, the first layer and the second layer of the cellular telephone network being coupled to the interface, wherein the second layer of the cellular telephone network transfers the payload information of the telephone call to and from the interface on a direct route assigned to the telephone call within the second layer.