7885 results about "Jitter" patented technology

A system and a method for controlling routing of data over multiple networks. Accordingly, network users can define specific flow polices to ensure that a particular flow of data traffic maintains an acceptable level of performance, such as in terms of latency, loss, jitter, or an acceptable level usage that includes cost and bandwidth management across multiple networks.

An improved data networking technique and apparatus using a novel physically distributed but logically shared and data-sliced synchronized shared memory switching datapath architecture integrated with a novel distributed data control path architecture to provide ideal output-buffered switching of data in networking systems, such as routers and switches, to support the increasing port densities and line rates with maximized network utilization and with per flow bit-rate latency and jitter guarantees, all while maintaining optimal throughput and quality of services under all data traffic scenarios, and with features of scalability in terms of number of data queues, ports and line rates, particularly for requirements ranging from network edge routers to the core of the network, thereby to eliminate both the need for the complication of centralized control for gathering system-wide information and for processing the same for egress traffic management functions and the need for a centralized scheduler, and eliminating also the need for buffering other than in the actual shared memory itself,—all with complete non-blocking data switching between ingress and egress ports, under all circumstances and scenarios.

An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition. A digital phase detector controls the delay line propagation delay to establish synchronization between the internal clock and the reference clock. Unused delay elements within the variable delay path are deactivated to save power.

In a complete network-in-a-box system acting as an enterprise network demarcation point, packets such as voice, video and data packets, are routed over common network connections, such as LAN and WAN. The packets are mapped from a public address field (such as an IP address) and port number to a private address field and port number, the mapping process typically being handled by a NAT (Network Address Translation). The packets are also prioritized, by marking the packets for priority queuing and routing, and configuring the bandwidths of the WAN traffic and the voice traffic to predetermined quantities and configuring the address fields of the voice devices. Simultaneous transmission of the various packets can be limited to predetermined quantities, typically by utilizing a CAC (Client Access Control). Secure firewalls are also included as well as a performance test client application that provides a defined workload generated across the WAN interface for capacity planning measurements and allows remote monitoring of the QoS (Quality of Service) data, such as latency, jitter, lost packets and MOS scores. Optionally, a simple, common remote management interface is included, allowing service providers to configure, upgrade and manage the system. Additionally, address fields can be provided to voice, video or data devices attached to a LAN port. VPN authentication and encrypted sessions can be tunneled through the firewall for access to an internal network by using a VPN terminator. For power outages and other emergency purposes, additional ports that connect to PSTN (Public Switched Telephone Network) analog telephone lines as well as other analog telephones or devices, can be provided. Another advantageous element is that most of the above components or features may be enabled or disabled.

An adaptive packet mechanism and method for optimizing data packet transmission through a network connection between a sending node and a receiving node. Current network conditions in the connection are periodically determined wherein the network conditions pertain to the latency and jitter of packet transmission between the sending node and receiving node. The measurements of latency and jitter are used to determine an optimum packet size and an optimum inter-packet interval for transmission of packet data between the sending node and the receiving node and are used in the transmission of data packets from the sending node to the receiving node. Network conditions may be determined by transmission of monitor or data packets and may be determined at either or both of the sending or receiving nodes and the optimum packet size and inter-packet interval are determined by a fuzzy logic analyzer, a neural network analyzer or a combined fuzzy logic / neural network analyzer.

An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition. A digital phase detector controls the delay line propagation delay to establish synchronization between the internal clock and the reference clock. Unused delay elements within the variable delay path are deactivated to save power.

A system for testing a segment of a data-packet-network has a first probe connected substantially at one end of the segment; a second probe connected substantially at the opposite end of the segment from the location of the first probe; and a process application distributed to each probe. The first and second probes collect data from and time stamp data packets as they pass forming first and second records of the individual packets whereupon the second-formed records of each packet are compared with the first records of each packet for record matching, time-stamp comparison and test result processing.