54 results about "Interleaving" patented technology

Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.

Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

The present application relates to the field of communication technology, and discloses an interleaving method and device, which are used to reduce the complexity of implementing Polar code interleaving and rate matching. The method is as follows: obtain the coded bits encoded by the Polar code, sort the coded bits according to the priority order of performing the rate matching operation, and obtain a first bit sequence, and the first bit sequence includes j subsequences, and j is positive integer, write the first bit sequence into the interleaver of row i and column j, wherein the bit in one column in the interleaver contains one subsequence in the j subsequences, and from the interleaver The bits are read out column by column until M bits are read, wherein at least two adjacent columns read in opposite directions, and M is the target code length.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbolsof the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded databetween the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively,during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to providethe a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuitan arbitrarily parallel turbo decoder.

The invention discloses a DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture and a decoding method. The DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture mainly comprises a serial-to-parallel conversion module, an input cache module, a variable node updating module, an interleaver module, a node cache module and a check node updating module. Based on the quasi-cyclic characteristic of a DVB-S2 standard IRA-LDPC code, the two-dimensional interleaving can be realized only by performing the inter-column interleaving and intra-column cyclic shift on an intermediate calculation result during parallel decoding, and the two-dimensional operation is simplified into two one-dimensional operation.

The present application discloses a concatenated encoding device, including: a first-level code interleaver and a second-level encoder. The first-level code interleaver includes a first cache and a second cache, wherein the first cache stores the information data at the current moment, and the second cache stores the data stored in the first cache at the previous moment; the first-level code interleaver will The mth row data in the first cache and the nth column data in the second cache are first-level encoded to obtain the mth check data, and the m check data is stored in the mth row of the first cache, wherein , both m and n are integers, and the value of m corresponds to the unique value of n; then the data in the first cache is interleaved according to the preset method to obtain the first codeword, and the second-stage encoder performs the first codeword The code word is encoded in the second stage to obtain the second code word and sent out. Wherein, the interleaving in the preset mode can reduce the bit error correlation between the code words generated by the two-stage encoding devices respectively.