49 results about "Interleaving" patented technology

A signal diversity method of an OFDM system comprises the following steps: carrying out data decoding, modulation and rotation-modulation by a transmitting end, and storing the symbols of the processed data blocks; subjecting the symbols of the data blocks of a plurality of users in a memory to grouping and time-frequency interleaving, OFDM time-frequency resource allocation and Q-path interleaving according to the set number of the users, respectively subjecting the symbols of each data block to IFFT operation and CP addition after zero padding according to the OFDM modulation length, then transmitting the data; and subjecting the symbols of the data blocks to de-CP and FFT operations after a receiving end receives the data, carrying out phase compensation and zero removal, and sequentially subjecting the symbols of the obtained data blocks to Q-path de-interleaving, rotation demodulation, time-frequency de-interleaving and coding to obtain the desired data information. By adopting OFDM technique and rotation modulation technique and by selecting an optimal rotation angle, the method can acquire signal diversity gain and maximal performance improvement, thereby improving the system performance.

A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

The invention discloses an interleaving and rate matching method. A correction interleaving mode is determined according to a column interleaving mode and head filling bits, an interleaving operator is determined according to the correction interleaving mode, and the interleaving operator is utilized to perform interleaving processing on subblock interleaving matrices in sequence; one mode can utilize the interleaving operator to perform the interleaving processing on bits required to be output in the subblock interleaving matrices according to the requirement of redundancy version, directly output subblock interleaving results after protocol sorting while completing the interleaving of subblocks until meeting the corresponding requirement of the code rate; and the other mode can utilize the interleaving operator to perform the interleaving processing on the subblock interleaving matrices one by one, output the subblock interleaving results after protocol sorting to a circulating buffer while completing the interleaving of subblocks, and then output corresponding bits after the interleaving according to the requirement of the redundancy version. Furthermore, the invention also discloses a de-interleaving and rate de-matching method corresponding to the interleaving and rate matching method. The methods can greatly reduce buffers to be used and read-write operation of the buffers in the interleaving and rate matching and de-interleaving and rate de-matching processes.

A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

The invention discloses a method for interleaving and deinterleaving a convolution in digital transmission. The method regards an RAM as a ring with end-to-end addresses, and occupies RAM I(I+1)M/2 space while interleaving according to the I and M information. While interleaving, the RAM is subject to writing-after-reading operations round by round. Differences among various addresses that are read and written in each round are M, 2M, to IM, and the address of the next round is close to that of the prior round. RAM I(I+3)M/2 space is occupied while deinterleaving, and reading-reading-writing operations are performed round by round. Differences among various addresses that are read for the first time in each round are (I+1)M, IM, to 2M, and the address of the next round is close to that of the prior round. The address that is read for the second time and the address that is read for the first time are separated by 2M+1 space, namely having a distance of the 2M (shown as in the figure). The written address is the same as the address that is read for the first time. The convolution process is simply controlled, and a deinterleaver and an RS decoder can share an RAM, which saves the resources.

Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N-G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N-G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N-G) bits.

The invention discloses an LDPC codeword interleaving and mapping method and an LDPC codeword de-interleaving and de-mapping method. The method comprises the following steps: performing bit interleaving of a coded LDPC codeword according to a certain bit interleaving method and an interleaving pattern; and performing constellation mapping of the bit interleaved LDPC codeword according to a constellation diagram so as to obtain a symbolic stream. According to the technical scheme provided by the invention, specific mapping and de-mapping methods are selected for an LDPC code having a specific code rate, such that the system performance is improved better.

A method and apparatus for autonomous, automatic interleaving of cycled loads coupled to a grid. In one or more embodiments, the method comprises (i) determining, by a smart load coupled to a grid, a first grid stress value; (ii) comparing, by the smart load, the first grid stress value to an activation threshold; (iii) waiting, by the smart load, when the first grid stress value is less than the activation threshold, a delay period; (iv) determining, by the smart load and after the delay period ends, a second grid stress value; (v) comparing, by the smart load, the second grid stress value to the activation threshold; and (iv) activating, by the smart load, when the second grid stress value is less than the activation threshold.

A multi-chip module includes a first integrated circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, and the first interleaved interconnections include a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, and the second interleaved interconnections include a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.

An apparatus and system for decreasing packet error rate (PER) in a station (STA) are described. The STA determines that an Extremely High Throughput (EHT) physical layer protocol data unit (PPDU) is to be constructed for transmission and that Low-Density Parity-Check (LDPC) encoding is to be used to encode a data field of the EHT PPDU. In response, the STA constructs the EHT PPDU in accordance with a construction constraint of the data field of the EHT PPDU when a LDPC codeword (CW) size 648 is to be used for the data field of the EHT PPDU. The construction constraint includes using bit level interleaving or preventing use of LDPC CW size 648 for a modulation coding scheme (MCS) that is larger than 256 quadrature amplitude modulation (QAM) or 64 QAM or for all QAMs.

The invention provides a time-frequency interleaving method based on block interleaving, a block interleaving method and a block interleaving system. The block interleaving method comprises the steps of: writing M*N pieces of input data into a matrix with M rows and N columns according to columns or written into a matrix with M columns and N rows according to rows; when the matrix with M rows and N columns is written according to the columns, sorting the row serial numbers of the matrix based on a first preset rule, and sequentially reading the data of each row according to the sorted row serial numbers; and when the matrix with M columns and N rows is written according to the row, sorting the column serial numbers of the matrix based on a second preset rule, and sequentially reading the data of each column according to the sorted column serial numbers. The time-frequency interleaving method based on block interleaving, the block interleaving method and the block interleaving system are not only suitable for scenes with N>1, but further suitable for scenes with N=1, and can effectively improve the block interleaving performance on the premise of not increasing communication overhead.

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.