115results about How to "Increase data bandwidth" patented technology

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

The invention discloses a VPX parallel DSP (Digital Signal Processing) board card based on SoC (System on a Chip) online reconstruction. An FPGA (Field Programmable Gate Array) chip is used as a board stage SoC controller; and two DSP chips are used as core operation chips of a DSP board card. During the practical configuration of the DSP chips, the FPGA chip used as the SoC controller can complete the dynamic re-configuration of work code by GE (Gigabit Ethernet) through the hardware resetting on the DSP and the switching on the starting mode; and the flexibility and the real-time performance during the DSP are greatly improved. The DSP chips receive two kinds of high-speed serial bus signals of SRIO (Serial Rapid Input Output) X4 and the GE transmitted through a VPX interface, repacking the transferred PCIE (Peripheral Component Interface Express) X2 high-speed serial bus signal through a PCIE exchange chip, and receives a data signal to be processed and a control instruction; or the DSP chips receive the GE protocol signal of a peripheral component through an RJ45 net port.

The invention discloses a Flash based PCIE (peripheral component interface express) board for data storage. The board is characterized in that an FPGA chip is used as the master control module, DDR memories are connected to serve as buffer modules and Flash chips are simultaneously connected to serve as storage modules; a PCIE controller, a DDR controller, a command parser, soft Cache hit logics,an X-Card management module, ECC check data logics, Flash block address mapping, an arbiter and a Flash controller are implemented inside FPGA and complete respective functions by downloading the programs to the FPGA. The communication interface adopts the PCIE interface which has high data transmission rate. PCI-E also supports advanced power management, hot plug and synchronous data transmission and optimizes the bandwidth for the preferentially transmitted data.

An electronic data transport system includes a mobile access point and a carrier for moving the mobile access point over a surface and/or water route. The mobile access point includes a communications module for wirelessly transmitting data to and receiving data from one or more client devices when the client device is in proximity to the mobile access point.

In certain embodiments, a wireless communication link includes a wireless receiver that receives a circular polarized signal from a remotely configured transmitter. The circular polarized signal has a polarization vector that rotates at a radial velocity. The wireless receiver determines a phase deviation in the radial velocity of the polarization vector and demodulates information from the circular polarized signal according to the determined phase deviation. The phase deviation is caused by a frequency deviation of the circular polarized signal generated by the transmitter.

The present invention is to contribute to reduction in cost of a system performing image recognition and display control on input image data. A data processor includes a central processing unit, a graphic controller, a display controller, an image recognizing module, a memory controller capable of controlling an access to an external memory, and image data input units for inputting image data from the outside and capable of performing necessary format conversion, and the components are formed on a single semiconductor substrate. The display controller performs display control on the image data read from the external memory via the memory controller. The image data input unit stores the image data input from the outside or the image data subjected to the necessary format conversion into a first area in the external memory via the memory controller. The image recognizing module or central processing unit executes an image process using the image data in the first area or image data in a second area, obtained by performing necessary data process on the image data, and stores a result of the process in a third area in the external memory.

The invention provides a memory controller based on the burst disorder memory access dispatching, which is used to the burst disorder memory access dispatching accessed by a memory, and comprises a reading-writing queue module for storing the reading-writing memory access from a processor in a two-dimension mode, a block arbitration module for arbitrating a burst memory access from each block in each memory clock period, and an event selection module for selecting the final memory access operation from the burst of each block after arbitrated to send to the memory. The block is conducted with the burst arbitration to dispatch the disorder memory access through changing the structure of a queue and adopting the priority expression provided by the invention, thereby increasing the data bandwidth of the memory, and reducing the executing time of the processor.

The invention discloses a high-power high-stability variable-load high-frequency acceleration system. The high-power high-stability variable-load high-frequency acceleration system comprises a low-level high-frequency controller, a power amplification and transmission system and a high-frequency cavity; the power amplification and transmission system comprises a high-frequency machine, a transmission line and a coupling window; the low-level high-frequency controller is responsible for generating low-level high-frequency signals with appropriate values, and driving the high-frequency machine by the generated low-level high-frequency signals; the high-frequency machine is responsible for amplifying the low-power high-frequency signals into high-power high-frequency electromagnetic waves, and then transmitting the electromagnetic waves to the coupling window through the transmission line; the coupling window is used for coupling high-frequency power from the amplification system to the high-frequency cavity, and is characterized in that the coupling window is a dynamic adjustable coupling window; the high-frequency cavity is of a runway cavity structure; the invention further discloses an automatic adjustment coupling degree algorithm of the high-power high-stability variable-load high-frequency acceleration system, wherein the algorithm comprises the steps that a dynamic reflection power adjustment coupling degree algorithm is initialized; and the final calculation formula of the dynamic reflection power adjustment coupling degree is obtained.