The invention belongs to the technical field of real-time adaptive
signal processing, particularly relates to an FPGA implementation device and method of an FBLMS
algorithm based on a
block floating point, and aims to solve the problem that conflicts exist among performance, speed and resources when an existing FPGA device implements the FBLMS
algorithm. The method comprises the following steps that an input cache transformation module performs block cache recombination on a reference
signal, converts the reference
signal into block floating points and then performs FFT transformation; a filtering module carries out filtering in a
frequency domain and carries out dynamic bit
cutting; an error calculation and output caching module performs block caching on the
target signal, subtracts the filtered output after the
target signal is converted into a
block floating point, and converts the result into a fixed-
point system to obtain a final cancellation result; and a
weight adjustment calculation module and a weight update storage module obtain the adjustment amount of the weight and update the weight block by block. Aiming at a recursive structure of the FBLMS
algorithm, a
block floating point data format and a dynamic bit
cutting method are adopted, so the data is ensured to have a
large dynamic range and high precision, conflicts among performance, speed and resources are solved,and the
reusability and expansibility are also improved through
modular design.