32 results about "Advanced Power Management" patented technology

Disclosed is a system providing tracking and wireless communications for remote diagnostics of a vehicle which transmits data communicated over a vehicle system's CAN bus to a remote location, which is adapted to use data received from a vehicle in order to compare the performance of the vehicle and / or of the operator of the vehicle with the performance of other vehicles and / or operators of other vehicles, which incorporates advanced power management functionality for conserving power, particularly when the system is disconnected from a main power supply, and which facilitates the identification of vehicles that have not reported back to the system or that have not moved within a specified time period.

Described is a method and system for power management of mobile computer displays, in which areas of the screen are selectively controlled to consume less power than other areas. For example, a foreground window having focus may receive normal brightness, while background areas are dimmed. To this end, the pixels of selected areas are controlled to vary color depth, resolution, refresh rate, brightness and / or the on / off state for any part of the display. Power settings for parts of the display not corresponding to a focused window can be gradually reduced over time. Power policy may determine which areas are given reduced power, and external mechanisms provide information useful in the determination, such as when the user last interacted with a window, where the mouse is hovering, explicit user instructions as to how to power manage a window, and sensors that detect where the user is likely to want more power.

Methods, systems, and non-transitory computer readable media for advanced power management for serial advanced technology attachment (SATA)-based storage devices are disclosed. According to one aspect, the subject matter described herein includes a method for advanced power management of SATA-based storage devices. The method includes, at a SATA-based storage device having a controller, a non-volatile memory for storing data, and a communication interface for communicating with a host, receiving from the host a command to enter a quiescent mode. In response to receiving the command to enter a quiescent mode, the storage device enters a quiescent mode. The storage device receives from the host an indication that the storage device should enter a low power mode. In response to this indication, the storage device puts at least a portion of the non-volatile memory into a low power mode while maintaining at least a portion of the controller in normal power mode. The storage device optionally puts a physical layer interface of the storage device into a low power mode for additional power savings.

A power management PC expansion card controller that includes power on reset circuitry to reset power management enable registers during a reset period, thereby ensuring that the PME registers correctly identify the power management capabilities of the controller. Once the PME registers are reset, an instruction may be provided to change the state of the registers from a default reset state to a state that supports advanced power management capabilities, for example wake-up functions. Additionally, the controller includes blocking circuitry to block conventional reset signals from resetting the power management and proprietary registers if the PME register is instructed to change states, thereby preserving the data contained in the power management and proprietary registers against future reset events. The controller of the present invention supports advanced power management specifications without requiring additional pinout arrangement or reassignment of pin functionality, so that the controller of the present invention can be implemented in current computer system without a the need for retooling or re-layout of system board circuitry and wiring diagrams.

An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor / cores. When the processor / cores have advanced power management systems, a sleep inhibit signal can be applied to the processor / core state machine preventing the state machine from entering a lower power state. The parameters of the processor / core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

The invention discloses a Flash based PCIE (peripheral component interface express) board for data storage. The board is characterized in that an FPGA chip is used as the master control module, DDR memories are connected to serve as buffer modules and Flash chips are simultaneously connected to serve as storage modules; a PCIE controller, a DDR controller, a command parser, soft Cache hit logics,an X-Card management module, ECC check data logics, Flash block address mapping, an arbiter and a Flash controller are implemented inside FPGA and complete respective functions by downloading the programs to the FPGA. The communication interface adopts the PCIE interface which has high data transmission rate. PCI-E also supports advanced power management, hot plug and synchronous data transmission and optimizes the bandwidth for the preferentially transmitted data.

A wheel alignment head and system that utilizes advanced power management to reduce non-essential power consumption for extended operating time between charges. The wheel alignment head is operable in a first operating state and a second operating state that consumes less power than the first operating state. In response to the occurrence of at least one predetermined event, the wheel alignment head switches its operation from the first mode of operation to the second mode of operation.