35 results about "High-level design" patented technology

A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

A method of generating a high level design of a distributed system test bed comprising the steps of defining a meta-model of the test bed; defining at least two architecture modelling elements within the meta-model to form an architecture model associated with the meta-model; defining at least one relationship between a pair of architecture modelling elements; defining properties associated with at least one of the architecture modeling elements; and storing the high level design in computer memory.

An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.

A circuit design method and a circuit design apparatus of this invention allow a judgement from a broader view based on high-level design information inputted upon a logic design to determine a rough packaging design. A rough placement position of a function block cell, which can configure a circuit that is an object of the design, unit on a circuit is determined on the basis of abstract circuit information in an abstract level higher than that of packaging design basic cell obtained in a logic design. On the basis of the rough placement position and the abstract circuit information, the function block cell is two-dimensionally developed into the packaging design basic cell, and a packaging design of the circuit that is an object of the design is performed. The method and apparatus of this invention is applicable to a design of a circuit such as an LSI, a PWB, etc.

The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

A system for, and method of, automatically generating a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a graph generator that parses a High-level Design Language (HDL) file to generate an intermediate graph containing definitions of microprocessor-accessible registers, node interrelationships and summary bits and masks associated with alarm registers, (2) a graph converter, associated with the graph generator, that selectively adds virtual elements and nodes to the intermediate graph to transform the intermediate graph into a mathematical tree and (3) a description generator, associated with the graph converter, that employs the mathematical tree to generate a static tree description in a programming language suitable for use by a device-independent condition management structure.

A system for, and method of, automatically generating a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a graph generator that parses a High-level Design Language (HDL) file to generate an intermediate graph containing definitions of microprocessor-accessible registers, node interrelationships and summary bits and masks associated with alarm registers, (2) a graph converter, associated with the graph generator, that selectively adds virtual elements and nodes to the intermediate graph to transform the intermediate graph into a mathematical tree and (3) a description generator, associated with the graph converter, that employs the mathematical tree to generate a static tree description in a programming language suitable for use by a device-independent condition management structure.

One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable fabric. The system uses this description of the mask-programmable cell to generate a derived library containing cells that can be obtained by programming the mask-programmable cell. Next, the system receives a high-level design for the integrated circuit. The system then performs a synthesis operation on the high-level design to generate a preliminary netlist for the high-level design, wherein the preliminary netlist contains references to cells in the derived library. Finally, the system converts the preliminary netlist into a netlist that contains references to the mask-programmable cell with the logic appropriately programmed. The netlist is then placed and routed with the mask programmable constraints on the mask programmable fabric. The design, thus implemented on the programmable fabric, can be changed to accommodate logic revisions and bug fixes by changing only a few masks required for its fabrication.

A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from “verification friendly” library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support “assume” and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.

The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time- domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

The invention provides a static maturity measuring method for an architecture. Cyclomatic complexity number, fan-in fan-out complexity, coupling between object, response for component and component cohesions on high-level design are obtained by applying the traditional object-oriented software evaluation method to the architecture level and using a component diagram of the architecture as a measurement object, and the information is further processed to obtain the static maturity of the architecture. The method can assist a user in discovering the problems in the static organization structure and the logic dependent relation of the architecture and improve the quality of the architecture.

Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

The invention discloses an adjustable band-pass filter based on a cross-coupling structure, which relates to the field of radio frequency devices. The present invention includes a dielectric substrate with a metal microstrip structure on the top surface and a metal grounding plate on the bottom surface. The metal microstrip structure includes two symmetrically arranged feed lines and four adjustable A tuned resonator, the present invention realizes that the fourth-order adjustable bandpass filter has a constant absolute bandwidth through a rational design structure, and the filter realizes a symmetrical transmission zero point based on a cross-coupling structure, which can effectively improve the frequency selectivity, and the present invention also It can effectively reduce the insertion loss in the adjustment range and improve the higher attenuation characteristics in the stop band. The filter provided by the invention has practical significance in being applied to high-order design and synthesis.

The invention discloses a jacking device and a method for improving the horizontal bearing performance of a low bearing platform, belonging to the technical field of bridge engineering. The jacking device can squeeze the soil of the side wall of the low cap and refill the dense crushed stone concrete, which solves the problem that the foundation soil of the side wall of the low cap is loose and cannot be in close contact with the side wall of the cap and cannot provide high-level resistance Therefore, the purpose of significantly improving the horizontal bearing capacity of low caps is realized, and the safety reserve goal of improving the pile group foundation of low caps is achieved. After the soil is compressed, the device is reset by a reset device, and the main components can be taken out from the slot, so it can be reused, thereby significantly reducing the application cost of the pushing device. It provides an additional safety reserve for the large-scale low cap pile foundation of important projects, and makes it possible to consider the role of the low cap in the design process of the pile group foundation. Security applications play an important role.