693 results about "Hardware description language" patented technology

This invention provides assistance to a user in accessing network attached information sources. In one aspect, the invention is a method for intelligently routing a user query to information sources relevant to that query, extracting relevant data fields from received responses, and intelligently presenting the extracted data in order of estimated relevance. The system of this invention implements one or more steps of the method in a centralized or distributed manner on one or more network attached computers. Further, this invention provides a novel language and implementation that facilitates easily written and maintained descriptions of information source query and response formats.

Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. The standardized language is capable of handling instruction set extensions which modify processor state or use configurable processors. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

There is provided an information sharing processing method comprising the steps of a page display processing step for acquiring a file from a predetermined server on a network and displaying the file as a page, wherein the file is described in a predetermined page description language and includes a description of link information to another file on the network; a common-screen display processing step for displaying an icon representing a user at a position on a common screen shared with the user and displaying a message issued by the user making an access to the same page as the page displayed at the page display processing step, wherein information on the position and the message are specified by the user in shared data transmitted by the user by way of a shared server on the network; and a screen superposition processing step for superposing the common screen displayed at the common-screen display processing step on the page displayed at the page display processing step. Accordingly, it is possible to make an access to the web page with ease while participating a chat. In addition, any one of the users is capable of immediately knowing whether the other user is making an access to the same web page.

A business-to-business application service provider includes an Internet website and webserver with EDA-on-demand solutions for system-on-a-chip designers. Such website allows electronic designs in hardware description language to be uploaded into a front-end EDA design environment. A behavioral model simulation tool hosted privately on the webserver tests and validates the design. Such tool executes only in the secure environment of the business-to-business application service provider. The validated solution is then downloaded back over the Internet for a pay-per-use fee to the customer, and in a form ready to be placed and routed by a back-end EDA tool. Such validated design solutions are also downloadable to others in exchange for other designs, or available in technology libraries. The intellectual property created can be re-used, sold, shared, exchanged, and otherwise distributed efficiently and easily from a central for-profit clearinghouse.

A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.

A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.

A method, system, and data structure for incorporating random instrumentation logic within a simulation model. The data structure of the present invention includes a first field containing data representing an assigned target and a second field containing data representing a logic value to be assigned to the assigned target. The first field and the second field are incorporated within a comment line of a design target entity source code file. A pre-pended comment identifier field identifies the data structure as a hardware description language comment.

The invention relates to the medical slice imaging and nuclear-imaging field, in particular to a first-group board card, a signal buffering unit, a second-group receiving board card, a data buffering unit, a reference clock 17, a clock adjusting unit and an on-site programmable gate array that are used for a conforming system in a positron slice scanning device; the method is characterized in that the on-site programmable gate array is utilized to judge the time, the position and the energy among all matters, and two matters that pass through the judging and selecting regulations form a conforming case. By inducting the on-site programmable gate array, the case information captured by a front-end detector module of a PET apparatus can be processed fast and high-efficiently by compiling hardware description language, so as to ensure whether the conforming matters happen or not. The method is an improvement of the process of the prior PET conforming system. The method can finish the process of the conforming system high-efficiently and fast by using a piece of FPGA and can lead the system not to be inducted into the dead time while the high system sensitivity is obtained.

The present invention is directed to a method and system for translating a high-level language (HLL) code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL which requires no modification in the original HLL source code, while supporting a cross call between software and hardware, and even recursive calls in hardware. The system includes: a HLL-to-HLL source translator which reads user programming directive from a translation-targeted high-level language code marked with the user directive, and separates the translation-targeted high-level language code into a hardware code part and a software code part; a main compiler which compiles the software code part; a HLL-to-HDL translator which includes the front-end and middle-end of the main compiler and a HDL backend; a main core which executes the compiled software code part; and a dedicated hardware which executes the HDL code.

Methods, systems and computer program products are disclosed for automatically generating hardware description language code from a model. The hardware description language code may be generated from a graphical program/model, such as a block diagram model. The hardware description language code may also be generated from a text-based program/model, such as a model created using MATLAB® tools. In particular, the present invention provides for the automatic code generation of an interface between components in the model. The present invention may provide options for selecting at least one of multiple types or styles of the component interfaces in the model. The selection of the interface types or styles may be controlled by the user or inferred by other parameters, such as implementation parameters.

An automated system-on-chip (SOC) hardware and software cogeneration design flow allows an SOC designer, using a single source description for any platform-independent combination of reused or new IP blocks, to produce a configured hardware description language (HDL) description of the circuitry necessary to implement the SOC, while at the same time producing the development tools (e.g., compilers, assemblers, debuggers, simulator, software support libraries, reset sequences, etc.) used to generate the SOC software and the diagnostics environment used to verify the SOC.

A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. Different accessor functions are used depending on which type of memory is used. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).