61 results about "Register transfer" patented technology

A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. Different accessor functions are used depending on which type of memory is used. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

A device for predistorting a transmission signal to be transmitted over a nonlinear transmission path comprises an estimator for determining an error signal depending on the transmission signal and a previously registered transfer characteristic of the nonlinear transmission path. The error signal represents an estimate of an error generated due to the nonlinearity of the trans-mission path. A time-dispersive element is provided to produce a correction signal by a temporal extension of the error signal. A combiner is provided to combine the transmission signal and the correction signal. As a result of the temporal extension of the error signal, an error signal segment in the frequency spectrum of a transmission signal transmitted by the nonlinear transmission path is shifted away from the useful frequency range of the transmission signal.

A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.

Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

In one aspect of the present invention, a bus buffer is provided. The bus buffer includes at least one buffer group having first and second groups of control input terminals. The first and second groups of control input terminals control different operational characteristics of the buffer group. The bus buffer includes first and second capture registers and first and second update registers. The data output terminals of the first update register are connected to the first group of control input terminals. The data output terminals of the second update register are coupled to the second group of control input terminals. The data input terminals of the first and second update registers are coupled to the data output terminals of the first and second capture registers, respectively. The bus buffer includes a new settings register having data output terminals coupled to the data input terminals of the capture registers.

A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.

A transfer pulse generator circuit for outputting a vertical register transfer pulse includes transfer pulse control means for controlling to set rise and fall timings of the vertical register transfer pulse to desired timings in a predetermined period.

A switch for use with an InfiniBand network. The switch includes a hub that redirects packets from a first InfiniBand device to a second InfiniBand device, a buffer that receives packets from the first InfiniBand device, and plurality of ports for transferring the data to the hub. A plurality of registers are coupled to the buffer for storing data from the packets. A switch network for selectively connecting the registers to the ports such that each register transfers a different portion of the data to a selected port.

The invention relates to the technical field of chip design and manufacturing, in particular to a register transfer-level signal mapping construction method, device and equipment and a storage medium, and the register transfer-level signal mapping construction method comprises the following steps: obtaining a register transfer-level code and a netlist-level code corresponding to the register transfer-level code; constructing a circuit according to the register transfer level code and the netlist level code; dividing the circuit into a plurality of modules according to grammar of the circuit in a hardware description language; determining a corresponding relationship between the modules by adopting a logic verification method; acquiring a register transmission level signal of which the mapping relation is to be constructed; and determining a netlist-level signal corresponding to the register transmission-level signal according to a module corresponding relationship. The mapping relation between the signals in the register transmission level codes and the signals in the netlist level codes is established directly according to the signals in the register transmission level codes, the implementation is simple, the cost is low, and modification of chips after logic synthesis is facilitated.

A horizontal register transfer pulse generator includes: phase adjuster generating an output signal, from reference signal; and horizontal blanking period generator based on output signal, reference signal, and horizontal blanking pulse, wherein horizontal blanking period generator includes: delay masking pulse generator generating delay masking pulse delayed by predetermined phase relative to masking pulse generated on horizontal blanking pulse inputted into horizontal blanking period generator; and determination means determining phase difference between output signal and reference signal, when phase difference between output signal and reference signal is less than predetermined phase, horizontal blanking period generator combines masking pulse with output signal to generate horizontal register transfer pulse with horizontal blanking period, and when phase difference between output signal and reference signal is equal to or greater than predetermined phase, horizontal blanking period generator combines delay masking pulse with output signal to generate horizontal register transfer pulse with horizontal blanking period.

The invention discloses a static superscale DSP cycle simulation method. A static superscale DSP cycle simulation system including an instruction preparation module and an instruction execution module is constructed; the instruction preparation module sets an initial value, acquires an instruction, determines the number of deferred cycles, determines the number of pause cycles and simulates clock propulsion; the instruction simulation module executes function simulation; a mathematical model of a superscale DSP cycle state is constructed from the view of time sequence; by time sequence simulation, an accurate state in a cycle when a DSP assembly line is paused; time sequence calculation mainly includes seeking of a maximum or minimum value and intersection operation which can be efficiently realized by bitwise operation; therefore, copying expense on a large number of register transfer levels and search expense on a register dependency sheet are avoided; the simulation calculation amount is relatively low, and the problems that a superscale DSP simulation method is inaccurate and relatively low in speed during DSP real-time software simulation test at the present are solved.