Flexible Microprocessor Register File

Abstract

Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I / O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Description

BACKGROUND AND SUMMARY[0001]The present application relates to programmable circuits, and more particularly to I / O circuitry with selectable data reordering for graphics.[0002]A vector processor or array processor is a CPU design that is able to run mathematical operations on multiple data elements simultaneously. A serial vector is a sequence of data held in registers that are processed by the same instruction. For example, a single instruction may cause four registers to be added to another four and the result written to a further four. A parallel vector holds several data items within the same register, each of which ahs the same instruction applied to it. Vector processing improves code density and allows optimizations that improve performance.[0003]A common problem suffered by vector processors is the need to organize data within the register file such that the same instruction may be applied to a series of registers. Register files generally only allow simultaneous access to a...

AI Technical Summary

Benefits of technology

[0002]A vector processor or array processor is a CPU design that is able to run mathematical operations on multiple data elements simultaneously. A serial vector is a sequence of data held in registers that are processed by the same instruction. For example, a single instruction may cause four registers to be added to another four and the result written to a further four. A parallel vector holds several data items within the same register, each of which ahs the same instruction applied to it. Vector processing improves code density and allows optimizations that improve performance.

[0007]The present application discloses a register file input / output configuration in which a variety of data transpositions are available at minimum power. Power is conserved by avoiding register-to-register data transfers; instead, the sequencer provides executable microinstructions which imply a variety of apparent data formats (as seen by the data channel), without unnecessary physical transfers of data.

[0008]Various disclosed embodiments provide new ways for microprocessor register-files to be accessible, in multiple formats in order to reduce the number of program instructions required during byte, word and long word data reformatting. The disclosed innovations, in various embodiments, provide one or more of at least the following advantages:

Problems solved by technology

A common problem suffered by vector processors is the need to organize data within the register file such that the same instruction may be applied to a series of registers.

It is common to spend several instructions re-arranging data to make it suitable for vector processing and this overhead may obviate the benefits of using a vector.

Yet another problem arises when a program instruction indirectly accesses a register.

Scoreboarding stalls these instructions, so the program need not manage stalling.

However, if a register is to be accessed indirectly by a program instruction, the register may not be known until it is too late—until after the stall condition would normally have already been applied.

Without knowing the register at that earlier time, it is difficult to apply stall conditions for instructions that use indirect access.

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