55 results about "Code density" patented technology

A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address / data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load / store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.

A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.

An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and processing logic for performing a sequence of operations on data including at least one re-arrangement operation. The processing logic has scalar processing logic for performing scalar operations and SIMD processing logic for performing SIMD operations. The SIMD processing logic is responsive to a re-arrangement instruction specifying a family of re-arrangement operations to perform a selected re-arrangement operation from that family on a plurality of data elements constituted by data in one or more registers identified by the re-arrangement instruction. The selected re-arrangement operation is dependent on at least one parameter provided by the scalar processing logic, that parameter identifying a data element width for the data elements on which the selected re-arrangement operation is performed. By such an approach, significant code density improvements can be made in respect of the code executed by the SIMD processing logic.

An image coding method is provided, in which the method includes the steps of: extracting edge information which represents an edge part of an original image; obtaining density information of an edge smoothed image from the original image by smoothing the edge part; obtaining coded edge information by coding the edge information according to a first coding algorithm; obtaining coded density information by coding the density information of the edge smoothed image according to a second coding algorithm; and sending the coded edge information and the coded density information as coded information to an image decoding apparatus.

An image coding method is provided, in which the method includes the steps of: extracting edge information which represents an edge part of an original image; obtaining density information of an edge smoothed image from the original image by smoothing the edge part; obtaining coded edge information by coding the edge information according to a first coding algorithm; obtaining coded density information by coding the density information of the edge smoothed image according to a second coding algorithm; and sending the coded edge information and the coded density information as coded information to an image decoding apparatus.

The invention discloses a no-chip tag structure, and the structure comprises a dielectric plate, wherein the surface of the dielectric plate is provided with at least one multi-ring nested paster unit. The multi-ring nested paster unit comprises a plurality of concentric annular pasters with different internal diameters and different external diameters. The structure provided by the invention aimsat the problems existing in the prior art, and the surface of the dielectric plate is flexibly provided with the multi-ring nested paster unit. The structure is small in size, is low in cost, is large in code capacity, and is high in code density.

The proposal relates to a complete system of long-range, high-density visual markers (marker design and detection method). In the design, a conventional location system for the long-range markers is used. The proposal therefore focuses on a system for coding information, which in this case is a colour-based code having four states, duplicating the code density with respect to conventional black-and-white systems. Moreover, the detection method requires very few computational resources, making it very efficient and especially suitable for mobile devices. To a great extent, the success of the technique lies in the methods proposed for the treatment of the colour.

The invention discloses a calibration method for inherent errors of TDC time interval measurement. An existing calibration method for the inherent errors of time interval measurement may increase thecomplexity of the whole measurement system structure and is poor in reconfigurability. The method disclosed by the invention includes the following steps: designing a random signal required for code density calibration according to the source of TDC inherent errors, wherein the random signal is composed of signals with different pulse widths and is used to simulate a time interval signal to be measured with a random width in actual measurement; and testing a delay chain by using the random signal to obtain a test sample, analyzing sample data to obtain a delay chain unit bit width error, and calibrating the delay chain unit bit width error. According to the scheme of the invention, a cyclic sequence of a random sequence can be ensured on the premise of preventing deadlock, and an originalcyclic sequence can be remained unchanged on the premise of adding an all-zero state.

The invention provides an image collecting control device and method. In practical instrument image collecting, the device drives an image collector located at the tail end of the device to change a collecting position by controlling a fixing support to move, and therefore instrument images of multiple instruments can be collected in sequence through one image collector, and the image collecting cost is lowered. A DSP is used for controlling the image collector to conduct image collecting, an ARM processor is used for achieving man-machine interaction, a servo power mechanism is controlled to adjust the moving track of the fixing support, and therefore the collecting position of the image collector is adjusted. It is clear that the control mode with the ARM and the DSP is adopted so that the image collecting control device can meet the practical requirements for the high code density, the high storage device utilization rate, the high control capability and the like.