418 results about "Instruction memory" patented technology

A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address / data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

A mobile phone or other personal communication device includes resources applying measures of an individual's hearing profile, personal choice profile, and induced hearing loss profile, separately or in combination, to build the basis of sound enhancement. A personal communication device thus comprises a transmitter / receiver coupled to a communication medium for transmitted receiving audio signals, control circuitry that controls transmission, reception and processing of call and audio signals, a speaker, and a microphone. The control circuitry includes logic applying one or more of a hearing profile of the user, a user preference related hearing, and environmental noise factors in processing the audio signals. The control circuitry may includes instruction memory and an instruction execution processor such as a digital signal processor.

A content search circuit for determining whether an input string matches one or more of a plurality of regular expressions, the content search circuit including an instruction memory for storing a plurality of microprograms, each microprogram embodying a corresponding one of the regular expressions, a control circuit having an input to receive the input string, and having a number of outputs, and a plurality of search engines, each having a first input coupled to a corresponding output of the control circuit and having a second input coupled to the instruction memory, wherein each search engine is selectable to execute any of the microprograms stored in the instruction memory to search the input string for any of the regular expressions embodied in the microprograms.

The present invention relates to a coupling node (MG1) for coupling of communications in a telecommunication system, comprising networks (N1, N2) with different signal formats. The coupling node has switching and trunking functions (CP21, CP23) corresponding to the signal formats, and telefunctions, e.g. coders / decoders (F21) and echo cancellers (F22), which the node can couple into a communication by means of a selector (PS1). The functions are supported by printed board assemblies (CB1–CB9) in magazines (SR1), and the printed board assemblies have signal processors (DSP11–DSP13) with access points (SAP11–SAP14). The selector hunts one of the signal processors for handling one of the functions. If the processor has sufficiently free memory space in its data store and in its instruction memory and sufficient processor capacity, this processor is selected. Otherwise a new processor is hunted which is investigated in the same way.

A mobile phone or other personal communication device includes resources applying measures of an individual's hearing profile, personal choice profile, and induced hearing loss profile, separately or in combination, to build the basis of sound enhancement. A personal communication device thus comprises a transmitter / receiver coupled to a communication medium for transmitted receiving audio signals, control circuitry that controls transmission, reception and processing of call and audio signals, a speaker, and a microphone. The control circuitry includes logic applying one or more of a hearing profile of the user, a user preference related hearing, and environmental noise factors in processing the audio signals. The control circuitry may includes instruction memory and an instruction execution processor such as a digital signal processor.

The invention provides an instruction set optimization method. In one aspect, the invention provides a microprocessor, which comprises: an instruction memory for mixed storage of first-length instructions and second-length instructions with different lengths, the first-length instructions are shorter than the second-length instructions and the two are distinguished by adopting operational codes; an instruction extraction unit, which extracts the instructions in mixed storage from the instruction memory and separates the first-length instructions from the second-length instructions according to the operational codes; an instruction decoding unit, which decodes the first-length instructions and the second-length instructions respectively; and a jump operation unit, which, in jump operation, transfers instructions to the boundary of either the first-length or the second-length instructions. By adopting the optimized instruction set, the program code size can be significantly reduced.

Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.

A processor implements an apparatus and a method for providing advance notice of an indirect branch address. A target address generated by an instruction is automatically identified. A next program address is prepared based on a most current target address before an indirect branch instruction utilizing the most current target address is speculatively executed. The apparatus suitably employs a register for holding an instruction memory address that is specified by a program as a most current indirect address of an indirect branch instruction. The apparatus also employs a next program address selector that selects the most current indirect address from the register as the next program address for use in speculatively executing the indirect branch instruction.

A device having at least one processor connected a controller and a memory; where the controller to execute a debug process. The debug process attaches a breakpoint bit field to each instruction. A system having image signal processors (ISPs), each ISP including processor elements (PEs). The ISPs include a debug instruction register connected to a first mux element. An instruction memory is connected to an instruction register. A decoder is connected to the instruction register. An execution unit is connected to the decoder. A debug executive unit is connected to the instruction memory, and a second mux element is connected to the execution unit and local registers. The decoder decodes a breakpoint bit field of each instruction.

The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (38), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.