2149 results about "Logical operations" patented technology

A graphical condition builder is provided that presents a graphical representation of a search query. In an embodiment, the graphical condition builder presents a graphical and numerical preview indicating the size of the expected query results set. In an embodiment, a graphical preview is provided that includes graphical preview portions having a shape suggestive of a funnel. In an embodiment, the graphical condition builder supports formulating queries for both relational and multidimentional databases. In an embodiment, the graphical condition builder displays a textual indication of the type of logical operation being performed. In an embodiment, the graphical condition builder determines the type of logical operator to apply depending on the relative location of icons representing filter objects. In an embodiment, order dependent filters are available to the user. In an embodiment, the search query is represented by query steps, and multiple filter objects may be contained in each query step.

Sensors detect machine parameters such as vibration, turning speed, and temperature, and a local processor performs logic operations based on the parameters and inference rules to produce fault information that is reported to a system processor, which selectively uses the fault information to control the plant machines. The inference rules include rules for determining faults as to balance, alignment, bearing condition, electrical condition, and cavitation. The inference rules are contained in rules code that is separate from the analysis code that performs the logical operations. Thus, the inference rules may be easily changed without changing other code, such as the analysis code.

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input / output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

A hierarchical arbitration method in which requests are grouped, using a logical OR operation for example, and provided to higher levels of the hierarchy. Then, grant signals from higher levels of the hierarchy are either propagated down through each level of the hierarchy where they are used to modify, using a logical AND operation for example, grant signals. Alternatively, grant signals from all higher levels of the hierarchy may be provided to a leaf layer of the hierarchy where they are all used to modify, using a logical AND operation for example, grant signals.

A database query optimizer processes an expression in a database query, and generates therefrom an operand list and a corresponding truth table that may be represented by a list of binary characters, where the operand list and corresponding truth table represent a disjunct normal form for the expression. Each expression is stored once it is processed into its operand list and corresponding list of binary characters. New queries are processed into component expressions, and each expression is checked to see if the expression was previously processed and stored as a processed expression. If so, the operand list and list of binary characters for the previously-stored expression may be used in processing the current expression. If there is no previously-stored expression that corresponds to the current expression, the previously-stored expressions are checked to see if any correspond to a complement of the current expression. If so, a new expression is easily constructed for the current expression by retrieving the list of binary characters that correspond to the complement expression, and inverting the bits in the list of binary characters. If there is no previously-stored expression that corresponds to the current expression or its complement, an operand list and corresponding list of binary characters are generated for the current expression. Logical operations between predicates in a query may be performed by performing mathematical operations on the lists of binary characters corresponding to each predicate expression. The end result is an operand list and corresponding list of binary characters that represents the entire expression in a query.

A system and method includes steps or acts of receiving and examining a computer program written in an object-oriented language; receiving sequences of accesses that form logical operations on a set of memory locations used by the program; receiving definitions of atomic sets of memory locations, each consisting of pieces of data; providing a message indicating where the synchronization is required.

A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.