Flash memory device capable of improving read performance

Abstract

A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2007-26658 filed on Mar. 19, 2007, the subject matter of which is hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to semiconductor memory devices. More particularly, the invention relates to flash memory devices executing cache read functions.[0003]Driven by ever-growing demands for higher performance contemporary memory systems including flash memory devices have incorporated a cache read functionality. During a cache read operation, previous read data stored in a cache register is output to an external circuit while current read data is read from memory through a main register. An exemplary cache read operation will be described with reference to Figure (FIG.) 1.[0004]Referring to FIG. 1, a read command, a corresponding read data address, and a read operation start indicat...

AI Technical Summary

Benefits of technology

[0007]In one embodiment, the invention provides a flash memory device comprising; a memory cell array configured to store N-bit read data, where N is a positive integer, a page buffer circuit comprising a page buffer configured to receive read data from the memory cell array during a read operation, wherein the page buffer comprises a main register transferring read data to a cache register during the read operation, and a control logic block configured to control operation of the page buffer during the read operation such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.

[0008]In another embodiment, the invention provides a method of performing a read operation in a flash memory device comprising a memory cell array; and a page buffer circuit comprising a page buffer, wherein the page buffer comprises a main register and a cache register, the method comprising; initiating operation of the main register, after transferring read data to the cache register, deactivating the main register, receiving a cache read command after deactivation of the main register, reactivating th...

Problems solved by technology

However, noise commonly associated with the provision of power voltages within the flash memory system occur during the output of the previous read data to the external circuit from the cache register.

In addition, noise associated with the initiation of main register operation is als...

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