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207results about How to "Minimum power consumption" patented technology

Novel massively parallel supercomputer

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:INT BUSINESS MASCH CORP

Home picture/video display system with ultra wide-band technology

A new display system and method is described, utilizing a cellular telephone having digital camera capability and a television linked directly over a UWB wireless signal forming a UWB wireless video pico-net. The system utilizes a digital camera unit to capture picture or video images for UWB transmission directly to the television acting as a pico-net host controller, either independently or together with the cellular telephone operating as a pico-net child. The display system comprises and one or more remote devices and a host display communicating on a UWB wireless network. The host display comprises a display for presentation of the picture or video images and a UWB transceiver for processing image data from the picture or video images, for selectively sending and receiving the image data based on a request from the child. The one or more remote devices comprise a digital camera for capturing the picture or video images and another UWB transceiver as used in the host display. The host display has a generally larger display for improved presentation of the captured picture or video images useful and amusing for group, party, wedding, and conference viewing, or simply for enhanced personal enjoyment. For picture or video image sharing, the system further facilitates downloading the current picture or video images from the host display television to a requesting cellular telephone or digital camera equipped with the UWB transceiver. The UWB display system provides sufficient bandwidth to support numerous such download requests simultaneously, while utilizing a transmission technology having minimal power consumption.
Owner:TEXAS INSTR INC

Home picture/video display system with ultra wide-band technology

A new display system and method is described, utilizing a cellular telephone having digital camera capability and a television linked directly over a UWB wireless signal forming a UWB wireless video pico-net. The system utilizes a digital camera unit to capture picture or video images for UWB transmission directly to the television acting as a pico-net host controller, either independently or together with the cellular telephone operating as a pico-net child. The display system comprises and one or more remote devices and a host display communicating on a UWB wireless network. The host display comprises a display for presentation of the picture or video images and a UWB transceiver for processing image data from the picture or video images, for selectively sending and receiving the image data based on a request from the child. The one or more remote devices comprise a digital camera for capturing the picture or video images and another UWB transceiver as used in the host display. The host display has a generally larger display for improved presentation of the captured picture or video images useful and amusing for group, party, wedding, and conference viewing, or simply for enhanced personal enjoyment. For picture or video image sharing, the system further facilitates downloading the current picture or video images from the host display television to a requesting cellular telephone or digital camera equipped with the UWB transceiver. The UWB display system provides sufficient bandwidth to support numerous such download requests simultaneously, while utilizing a transmission technology having minimal power consumption.
Owner:TEXAS INSTR INC

Massively parallel supercomputer

InactiveUS7555566B2Massive level of scalabilityUnprecedented level of scalabilityError preventionProgram synchronisationPacket communicationSupercomputer
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:IBM CORP

Process and systems

An apparatus for recovering energy from an osmotic system, said apparatus comprising: (i) a feed stream (143,251); (ii) pressure means (140,150, 250, 254) to pressurise said feed stream; (iii) a manipulated osmosis unit (110,220,230); (iv) an energy recovery unit (120, 240, 260) in fluid connection with second solution side of the manipulated osmosis unit; (v) a reverse osmosis unit (130) receiving a feed from the energy recovery unit.
Owner:AL MAYAHI ABDULSALAM +1

System and method for reducing power consumption for wireless communications by mobile devices

A power control scheme for a wireless network communication system that includes a base station and multiple wireless mobile device dynamically adjusts transmission power of a mobile device in conjunction with adjusting its bit allocation in source coding and channel coding to minimize its total power consumption while maximizing the system capacity in terms of the total effective transmission rates received by the base station. The base station sets a target signal quality value for each mobile station, and the target values are determined by the base station such that the total effective data rate from all the mobile devices is maximized under constraints of the total received power and the error protection level requirements for the mobile devices. The base station periodically measures a signal quality value, such as a signal-to-interference ratio (SIR), from transmissions received by the base from each mobile device, compares it with the measured signal quality value for that mobile device, and sends a control signal instructing the mobile device to increase or decrease its transmission power based on the result of the comparison. When the mobile device receives the control signal, it determines an amount of adjustment to its transmission power by performing a minimum calculation under constraints on the total data distortion and the maximum transmission rate to adjust the parameters for source coding, channel coding, and transmission under the constraints to result in a redistribution of power between the components that provides the minimized total power consumption.
Owner:MICROSOFT TECH LICENSING LLC

Amplifier using delta-sigma modulation

ActiveUS20050162222A1High SNDR performancePrevent harmonic distortionAnalogue conversionDc amplifiers with modulator-demodulatorGreek letter sigmaDelta-sigma modulation
An amplifier and a driver circuit therefor are presented for driving a load according to a system analog input. The amplifier comprises a passive delta-sigma modulator with a passive filter providing a first filtered signal according to a passive filter input and according to a feedback signal, a quantizer coupled with the passive filter and providing a quantized output according to the first filtered signal, and a switching system coupled with the the passive filter and the quantizer. The switching system selectively providing power to a load according to the quantized output and provides the feedback signal to the passive input, wherein a gain amplifier is provided in a feedback loop around the passive delta-sigma modulator.
Owner:TEXAS INSTR INC
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