Microprocessor bus structure and microprocessor

A technology of microprocessor and bus structure, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of low cost, slow data processing speed, and poor use of advantages, so as to improve efficiency and improve data transmission speed effect

Active Publication Date: 2011-05-04
HISENSE VISUAL TECH CO LTD
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, with the increasing requirements of various systems for the processing rate of the controller and the speed of information transmission, the traditional microprocessor has a slow data processing speed due to the bus limit, and the low transmission rate has become an important bottleneck restricting the microprocessor. The single-chip microcomputer is small in size, low in cost, and the advantages of easy integration cannot be fully utilized
In addition, the traditional microprocessor adopts a single-bus structure, and the instruction operands are time-division multiplexed on the bus, and the bus is used serially, which greatly reduces the execution speed of instructions.

Method used

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  • Microprocessor bus structure and microprocessor
  • Microprocessor bus structure and microprocessor
  • Microprocessor bus structure and microprocessor

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Embodiment Construction

[0019] The invention aims to provide a bus structure capable of increasing the internal data transmission speed of the microprocessor, so that the efficiency of the microprocessor can be effectively improved. For this reason, the present invention adopts the following specific implementation modes, and the specific technical solutions adopted by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0020] in figure 1 In the specific embodiment of the internal bus structure of the microprocessor shown in , the key point is: in the CPU of the whole microprocessor, the idea of ​​Harvard structure is adopted to decompose the single bus structure in the traditional microprocessor into multiple bus Structure, which separates the program bus from the data bus, and the data bus is further divided into the operand bus Databus and two register transfer buses RegbusA and RegbusB. After this design, data (instructions and operands) can b...

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Abstract

The invention relates to a common bus or bus system concerning a device in a decentralized access structure and chips adopting the common bus or the bus system, in particular to a bus structure in a microprocessor and a microprocessor adopting the bus structure. The bus in the microprocessor is in a Harvard structure, and the bus structure comprises a program bus for transmitting program commandsand a data bus for transmitting data, wherein the data bus further comprises an operand bus and at least one register transfer bus. By using the technical scheme, the bus structure provided by the invention can improve the transmission speed of data in the microcomputer, and the efficiency of the microprocessor can be effectively improved.

Description

technical field [0001] The present invention relates to a kind of common bus or the bus system of the device about distributed access structure, and adopt the chip of this bus or bus system, more specifically, refer to a kind of bus structure of microprocessor and adopt this bus structure of the microprocessor. Background technique [0002] Since the main working process inside the computer is the process of information transmission and processing, the data transmission between the various components inside the machine is very frequent. In order to reduce the number of internal transmission lines and facilitate control, the data transmission paths between some registers are usually merged to form a bus structure, so that information from different sources is time-divisionally transmitted on this transmission line. According to the location of the bus, the bus is divided into two types: internal bus and external bus. The internal bus refers to the connection of various comp...

Claims

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Application Information

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IPC IPC(8): G06F13/40
Inventor 李金亭
Owner HISENSE VISUAL TECH CO LTD
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