The invention provides a structure of a heterogeneous gate tunneling transistor of an under-gate process and a forming method of the heterogeneous gate tunneling transistor. The heterogeneous gate tunneling transistor comprises a substrate, a channel region, a source region, a drain region and a gate stack, wherein the channel region is formed in the substrate; the source region and the drain region are arranged on the two sides of the channel region; the doping types of the source region and the drain region are reverse; the gate stack is formed on the channel region and comprises a gate dielectric layer, a first gate electrode, a second gate electrode, a first vacuum side wall and a second vacuum side wall; the first gate electrode and the second gate electrode are formed on the gate dielectric layer and have different work functions; and the first vacuum side wall and the second vacuum side wall are formed on the two sides of the first gate electrode and the second gate electrode. Since the vacuum side wall from the gate to the drain region is introduced, the control of the gate over the drain region is weakened, and the gate-drain capacitance is reduced; a certain distance which can be accurately controlled exists between the gate stack and the drain region of a device, so that a tunneling potential barrier path is increased, and a double-pole window is expanded; and the energy band distribution of the channel region is modulated by a work function structure of the transverse heterogeneous gate, so that the sub-threshold slope of a transistor is obviously reduced, the driving current is increased and the performance of the device is enhanced.