3611results about How to "Reduce capacitance" patented technology

A TANK filter is provided for a lead wire of an active medical device (AMD). The TANK filter includes a capacitor in parallel with an inductor. The parallel capacitor and inductor are placed in series with the lead wire of the AMD, wherein values of capacitance and inductance are selected such that the TANK filter is resonant at a selected frequency. The Q of the inductor may be relatively maximized and the Q of the capacitor may be relatively minimized to reduce the overall Q of the TANK filter to attenuate current flow through the lead wire along a range of selected frequencies. In a preferred form, the TANK filter is integrated into a TIP and / or RING electrode for an active implantable medical device.

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a "keyhole" shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

A controller for use with a multi-segment electroluminescent display 1. Control signals C1–CN control a plurality of half H-bridges H and Hc, the terminals of the half H-bridges being connected respectively to ground and to a high voltage DC supply 9. One of said half H-bridges provides a common output Vcommon and the remaining H-bridges provide drive voltages V1–VN for the segments of the display. The H bridges are driven by an oscillator 14 so that an AC voltage is selectively applied to the segments of the display. A power supply 24 provides a predetermined amount of power per unit area of the display. This is controlled by an area summation engine 22 having a segment data input, a segment counter and a memory containing area data corresponding to the segment(s) of the display. Based on the input from the segment data input, the area(s) of the segment(s) that are to be lit are obtained from the memory and summed to provide the total area to be lit. This is fed to the power supply 24, which then feeds the correct amount of power to display 1 via the half H-bridges.