Neural network processor oriented automatic design method, device and optimization method

Abstract

The invention provides a neural network processor oriented automatic design method, device and optimization method. The automatic design method includes: a first step, acquiring a neural network model description file and a hardware resource constraint parameter, wherein the hardware resource constraint parameter includes the hardware resource size and the target operation speed; a second step, searching a unit library from an established neural network assembly library according to the neural network model description file and the hardware resource constraint parameter, and generating a hardware description language code corresponding to a neural network processor of the neural network model according to the unit library; and a step 3, converting the hardware description language code into a hardware circuit of the neural network processor.

Description

technical field [0001] The invention relates to the technical field of neural network processor architecture, in particular to an automatic design method, device and optimization method for neural network processors. Background technique [0002] The rapid development of deep learning and neural network technology provides new solutions for large-scale data processing tasks. Various new neural network models have excellent performance in dealing with complex and abstract problems. New applications in the field emerge in an endless stream. [0003] At present, the real-time task analysis using deep neural networks mostly relies on large-scale high-performance processors or general-purpose graphics processors. These devices have high cost and high power consumption. When they are applied to portable smart devices, they have large circuit scale, high energy consumption and expensive products. And so on a series of questions. Therefore, for energy-efficient real-time processin...

AI Technical Summary

Problems solved by technology

Under the same process conditions, ASIC chips run fast and consume low power consumption, but the design process is complicated, the casting cycle is long, and the development cost is high, which cannot adapt to the characteristics of rapid update of neural network models; FPGA has the characteristics of flexible circuit configuration and short development cycle. features, but the running speed is relatively low, and the hardware overhead and power consumption are relatively large

No matter which of the above hardware acceleration technologies is used, it is necessary for the neural network model and algorithm developers to understand the network topology and data flow mode while mastering the hardware development technology, including processor architecture design, hardware code writing, simulation verification, layout and wiring, etc. , these technologies are more difficult to develop for high-level application developers who focus on researching neural network models and structural design, but do not have hardware design capabilities

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