704 results about "PCI Express" patented technology

The present invention provides a motherboard that uses a high-speed, scalable system bus such as PCI Express® to support two or more high bandwidth graphics slots, each capable of supporting an off-the-shelf video controller. The lanes from the motherboard chipset may be directly routed to two or more graphics slots. For instance, the chipset may route (1) thirty-two lanes into two ×16 graphics slots; (2) twenty-four lanes into one ×16 graphics slot and one ×8 graphics slot (the ×8 slot using the same physical connector as a ×16 graphics slot but with only eight active lanes); or (3) sixteen lanes into two ×8 graphics slots (again, physically similar to a ×16 graphics slot but with only eight active lanes). Alternatively, a switch can convert sixteen lanes coming from the chipset root complex into two ×16 links that connect to two ×16 graphics slots. Each and every embodiment of the present invention is agnostic to a specific chipset.

An apparatus and method is provided for interfacing a number of computer servers (or operating system domains) to a network such as Ethernet through a shared network interface controller (NIC) which is part of the load-store architecture of the operating system domains. The network interface controller includes a bus interface to couple the controller to a load-store domain bus (such as PCI-Express), the bus including header information to associate data on the bus with an originating operating system domain. The controller also includes transmit / receive logic to connect it to the network. In between the bus interface and the transmit / receive logic is buffering to temporarily store data coming either from the operating system domains or the network. The buffered data is tagged within an identifier to associate it with one or more of the operating system domains. Association logic is further provided to allow the controller to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Descriptor Register files are also duplicated for each operating system domain. A number of direct memory access (DMA) engines are provided to improve throughput. And, packet replication logic, along with filters (perfect and hash) and VLAN tables are used for looping back packets originating from one of the operating system domains to one or more of the other operating system domains, for server to server communication, multicast and broadcast operations.

A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.

A universal routing identifier (URID) is provided to extend the function space in PCI-Express fabrics. Methods and systems based on the URID are provided for configuring URID capable devices and upgrading PCI-Express bridges and switches having lookup tables with access control functionality. The lookup table entry contains URIDs of destination ports, backup ports, acceptance ports, and permitted ports for downstream and upstream filtering, routing and arbitrating of transaction packets. URID capable devices can be incrementally added to current PCI-Express bridges and switches. A configuration mechanism is added to the current PCI / PCI-Express enumeration software. The URID capabilities can be disabled to maintain system compatibility. A URID capable PCI-Express system is able to address ten of thousands single-function devices. A URID capability segment field is provided in the current PCI-Express configuration space. Each URID capable device contains the URID capability segment implemented in its own set of configuration space registers.