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Decoding method based on dvb-s2 standard ldpc code parallel decoding fpga implementation architecture

A technology of DVB-S2 and LDPC codes, applied in the field of FPGA technology

Active Publication Date: 2020-12-11
南京中科晶上通信技术有限公司
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Problems solved by technology

[0003] There are still many problems in the existing solutions in terms of storage capacity and delayed processing

Method used

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  • Decoding method based on dvb-s2 standard ldpc code parallel decoding fpga implementation architecture
  • Decoding method based on dvb-s2 standard ldpc code parallel decoding fpga implementation architecture
  • Decoding method based on dvb-s2 standard ldpc code parallel decoding fpga implementation architecture

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Embodiment Construction

[0033] Such as figure 1 As shown, the FPGA implementation method of IRA-LDPC code parallel decoding based on DVB-S2 standard designed in this paper mainly includes the following parts: serial-to-parallel conversion (S2P), input buffer (RAM_L), variable node update (VPR), interleaving It is composed of six parts including device (It), node cache (RAM_P) and check node update (SPR).

[0034] (1) Serial-to-parallel conversion (S2P). Parallel storage control is performed on the serial decoding input. The front system codes are stored in parallel in 360 input buffers (RAM_L) in sequence, and the check codes are stored in serial in 360 input buffers (RAM_L) in sequence.

[0035] (2) Input cache (RAM_L). Consists of 360 independent memories (RAM), single input and single output, storing decoding input (likelihood ratio), and the storage depth of each memory is the code length divided by 360.

[0036] (3) Variable node update (VPR). It consists of 360 independent variable node upd...

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Abstract

The invention discloses a DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture and a decoding method. The DVB-S2 standard-based LDPC code parallel decoding FPGA implementation architecture mainly comprises a serial-to-parallel conversion module, an input cache module, a variable node updating module, an interleaver module, a node cache module and a check node updating module. Based on the quasi-cyclic characteristic of a DVB-S2 standard IRA-LDPC code, the two-dimensional interleaving can be realized only by performing the inter-column interleaving and intra-column cyclic shift on an intermediate calculation result during parallel decoding, and the two-dimensional operation is simplified into two one-dimensional operation.

Description

technical field [0001] The invention belongs to the field of new generation information technology, especially FPGA technology. Background technique [0002] In the DVB-S2 standard, the Irregular Repeat Accumulation (IRA) Low Density Check Code (LDPC) code is used as the channel coding scheme. Using IRA-LDPC can improve the coding gain on the one hand, and on the other hand, multiple channels can be used in parallel when decoding Decoding to improve the throughput of the system. The general decoding algorithm of LDPC is belief propagation (BP) algorithm, which is an iterative probability decoding algorithm. The BP decoding algorithm includes two main links of variable node update and check node update. In the parallel decoding algorithm, the intermediate calculation results between the two links need to be interleaved in two dimensions. [0003] There are still many problems in the existing solutions in terms of storage capacity and delayed processing. Contents of the in...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/1197
Inventor 王本庆赵峰母洪强张锐胡金龙
Owner 南京中科晶上通信技术有限公司
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