Improved DDR II dram data path

Abstract

An improved doubled data rate (DDR)-II type dynamic random access memory (DRAM) device data path is disclosed. Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a type of access mode (e.g., interleaved or sequential), and performing scrambling operations based on chip organization (e.g., x4, x8, or x16) a bank location being accessed. Through separation the high speed buffer logic from switching logic which can perform other various logic functions, the switching logic performing the functions can work under a lower clock frequency, thus the time that data is transmitted from the memory arrays to the DQ pads is saved and associated timing requirements is relaxed and the latency is improved, otherwise.

Description

technical field [0001] The present invention relates generally to accessing memory devices, and more particularly, to accessing double data rate (DDR) dynamic random access memory (DRAM) devices, such as DDR-II type DRAM devices. Background technique [0002] The development of submicron CMOS technology has led to an increase in demand for high speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Here, this type of memory is collectively referred to as a DRAM device. [0003] Some types of DRAM devices have a synchronous interface, which usually means that data is written to or read from the device along with clock pulses. Early synchronous DRAM (SDRAM) devices transferred one bit of data per clock cycle (eg, on the rising edge), and were properly referred to as single data rate (SDR) SDRAM devices. Later, improved double data rate (DDR) SDRAM devices included input / output...

AI Technical Summary

Problems solved by technology

Unfortunately, synthetic designs have disadvantages

For example, it typically puts all combinatorial logic together, which incurs larger gate delays and larger mask areas, which impacts performance and density

Also, timing disturbances and unnecessary switching operations in these designs often degrade speed performance and increase power consumption

These timing issues get worse as the clock frequency increases

Furthermore, the typically unsystematic nature of synthetic design logic does not facilitate reuse, for example, across device family members with different architectures (e.g., ×4, ×8, and ×16) or within individual devices supporting different architectures

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