Memory device and method for exchanging data with memory device

Abstract

Improved double data rate type II dynamic random access memory data path. The present invention proposes techniques and circuits to support the switching operations required to exchange data between a memory array and an external data buffer. In the write path, this switching operation can include latching and assembling some of the data bits received sequentially on a single data buffer, rearranging the data bits based on the type of access pattern (for example, interleaved or sequential). Sort and perform encoding operations on the accessed bank locations based on the chip structure (eg ×4, ×8, ×16). Similar operations are performed in the read path (in reverse order) to assemble the data to be read from the slave device. By separating the cache logic from the switching logic that can perform various other logic functions, the switching logic that performs those functions can operate at a lower clock frequency, saving the time of data transfer from the memory array to the DQ buffer, which can Alleviate the associated timing needs and improve latency, and vice versa.

Description

technical field [0001] The present invention relates generally to accessing memory devices, and more particularly, to accessing double data rate (DDR) dynamic random access memory (DRAM) devices, such as DDR-II type DRAM devices. Background technique [0002] The development of submicron CMOS technology has led to an increase in demand for high speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Here, this type of memory is collectively referred to as a DRAM device. [0003] Some types of DRAM devices have a synchronous interface, which usually means that data is written to or read from the device along with clock pulses. Early synchronous DRAM (SDRAM) devices transferred one bit of data per clock cycle (eg, on the rising edge), and were properly referred to as single data rate (SDR) SDRAM devices. Later, improved double data rate (DDR) SDRAM devices included input / outpu...

AI Technical Summary

Problems solved by technology

Unfortunately, synthetic designs have disadvantages

For example, it typically puts all combinatorial logic together, which incurs larger gate delays and larger mask areas, which impacts performance and density

Also, timing disturbances and unnecessary switching operations in these designs often degrade speed performance and increase power consumption

These timing issues get worse as the clock frequency increases

Furthermore, the typically unsystematic nature of synthetic design logic does not facilitate reuse, for example, across device family members with different architectures (e.g., ×4, ×8, and ×16) or within individual devices supporting different architectures

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