IC die to IC die interconnection using error correcting code and data path interleaving

Abstract

A multi-chip module includes a first integrated circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, and the first interleaved interconnections include a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, and the second interleaved interconnections include a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.

Description

[0001] Related Applications Cross Application [0002] The title of the invention submitted by this application on September 12, 2018 is "IC Die To IC Die Interconnect Using Error Correcting Code And Data Path Interleaving" Priority to U.S. Provisional Patent Application Serial No. 62 / 730,048, which is hereby incorporated by reference as if reproduced herein in its entirety. technical field [0003] The present application relates to integrated circuit (IC) technology, and more particularly to communication between IC dies of a multi-chip module. Background technique [0004] Integrated circuit (IC) technology has made great progress over the past fifty years. ICs are now ubiquitous and found in electronic equipment, machines, vehicles, appliances and many other devices. Large processing ICs now include billions of transistors, while memory ICs include hundreds of billions of transistors. The density of transistors on an IC can reach 100 million transistors per square mil...

AI Technical Summary

Problems solved by technology

However, as bond pads are doubled for redundancy, the silicon area of ​​the bond pad array increases proportionally to redundancy, resulting in high silicon area cost, additional power dissipation from high capacitive loads, and resulting in heat generation increase

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