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6473results about "Baseband system details" patented technology

Novel massively parallel supercomputer

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:INT BUSINESS MASCH CORP

Breaker box powerline communication device

A Power Line Communications (PLC) device includes a processing module, memory, and a plurality of PLC communication interfaces coupled to the processing module. Each PLC communication interface couples to a respective PLC media segment. The processing module, the plurality of PLC communication interfaces, and the memory are operable to receive a PLC communication from a first PLC device via a first PLC communication interface of the plurality of communication interfaces, process the PLC communication to identify a second PLC device, and transmit the PLC communication to the second PLC device via a second PLC communication interface of the plurality of communication interfaces. The PLC device may include one or more non-PLC interfaces that support non-PLC communications.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Improving signal integrity in differential signal systems

Over-terminating the differential mode impedance of a differential transmission line, such as an INFINIBAND™ cable, at the receiving end, improves the differential signal integrity for typical variations in termination network impedance component (e.g., resistor) and transmission line characteristics. Eye opening of the differential signal can be made larger with reduced attenuation but increased jitter compared to under-terminating the differential mode impedance. Because the differential signal quality (larger eye opening) is improved, data can be transmitted over a longer transmission line with the same transmitter and receiver.
Owner:VALTRUS INNOVATIONS LTD

Signal transmission apparatus and interconnection structure

Apparatus for transmitting a digital signal within, for example, an integrated circuit includes a signal transmission line with a directional coupler at one or both ends. The directional coupler blocks the direct-current component of the digital signal while transmitting the alternating-current component, including enough higher harmonics to transmit a well-defined pulse waveform. A suitable directional coupler consists of two adjacent line pairs in materials with different dielectric constants. The apparatus may also include a driver of the inverter type, a receiver of the differential amplifier type, a terminating resistor, and a power-ground transmission line pair for supplying power to the driver. An all-metallic transmission-line structure is preferably maintained from the output interconnections in the driver to the input interconnections in the receiver.
Owner:PANASONIC CORP +11

System and method for transmission-line termination by signal cancellation, and applications thereof

An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which sensesthe signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments. In another embodiment, line receiver functionality is integrated into the SCU, designated as a Signal Canceling and Receiving Unit (SCRU) (90). The SCRU can perform all the SCU functions, and also serves as a line receiver in the communication network. In yet another embodiment, line driver functionality is integrated into the SCRU, designated as a Signal Canceling, Receiving and Transmitting Unit (SCRTU) (120). The SCRTU can perform all the SCRU functions, and also serves as a line driver in the communication network. Upon connecting multiple SCRTU's to a continuous transmission line, terminated independent point-to-point communication segments are formed.
Owner:CONVERSANT INTPROP MANAGEMENT INC

Code division multiple access (CDMA) communication system

A multiple access, spread-spectrum communication system processes a plurality of information signals received by a Radio Carrier Station (RCS) over telecommunication lines for simultaneous transmission over a radio frequency (RF) channel as a code-division-multiplexed (CDM) signal to a group of Subscriber Units (SUs). The RCS receives a call request signal that corresponds to a telecommunication line information signal, and a user identification signal that identifies a user to receive the call. The RCS includes a plurality of Code Division Multiple Access (CDMA) modems, one of which provides a global pilot code signal. The modems provide message code signals synchronized to the global pilot signal. Each modem combines an information signal with a message code signal to provide a CDM processed signal. The RCS includes a system channel controller is coupled to receive a remote call. An RF transmitter is connected to all of the modems to combine the CDM processed signals with the global pilot code signal to generate a CDM signal. The RF transmitter also modulates a carrier signal with the CDM signal and transmits the modulated carrier signal through an RF communication channel to the SUs. Each SU includes a CDMA modem which is also synchronized to the global pilot signal. The CDMA modem despreads the CDM signal and provides a despread information signal to the user. The system includes a closed loop power control system for maintaining a minimum system transmit power level for the RCS and the SUs, and system capacity management for maintaining a maximum number of active SUs for improved system performance.
Owner:INTERDIGITAL TECH CORP

Synchronous processing method based on CMMB signals

The invention provides a synchronous processing method based on new CMMB (China Mobile Multimedia Broadcasting) synchronous signals. The CMMB synchronous signals comprise first training sequences and second training sequences; the first training sequences comprise CAZAC (Constant Amplitude Zero Auto Correlation) sequences, and the second training sequences comprise PN (Pseudo-Noise) sequences; in the synchronous processing method, the CAZAC sequences are utilized to achieve coarse symbol timing offset estimation and decimal frequency offset coarse estimation; the PN sequences are utilized to achieve the estimation of strongest path time delay in multipath, and the multipath is taken as coarse symbol timing positioning; the CAZAC sequences and the PN sequences are utilized to achieve the integer frequency offset estimation; the fast Fourier transform (FFT) is performed on the PN sequences to achieve the channel response estimation so as to estimate a first path time delay and achieve the fine symbol timing position estimation; and a maximum likelihood (ML) criterion is utilized to process the PN sequences in the second training sequences to obtain the decimal frequency offset fine estimation. The synchronous processing method can effectively improve the synchronous accuracy and can achieve better synchronization performance in the mobile communication environment with low signal-to-noise ratio.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

Massively parallel supercomputer

InactiveUS7555566B2Massive level of scalabilityUnprecedented level of scalabilityError preventionProgram synchronisationPacket communicationSupercomputer
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:IBM CORP

UWB dual tunnel diode detector for object detection, measurement, or avoidance

A highly sensitive, high-speed dual tunnel diode detector is described for use in Ultra Wideband (UWB) object detection systems, such as a radar. The extended capability of the detector to both extremely short (sub-foot) and long distance (tens of thousands of feet) ranges is unique and permits the application of low power UWB radar to a wide variety of applications including high resolution radar altimetry at altitudes exceeding 10,000 feet and for autonomous on-deck landing operations (e.g., one-foot altitudes), the detection of extremely low radar cross section (RCS) targets for such applications as suspended wire detection for helicopters and other manned and unmanned craft, etc. High noise and interference immunity of the detector permits co-location of a UWB radar sensor with other active systems. The invention has immediate and significant application to all areas, both military and commercial, of precision distance measurement, intrusion detection, targeting, etc. over a wide range of distances.
Owner:ZEBRA TECH CORP
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