52 results about "Digital delay locked loop" patented technology

A digital delay locked loop (DLL) includes a coarse delay segment and fine delay segment. The coarse delay segment includes a coarse delay range. The fine delay segment includes a fine delay range. The coarse delay segment and the fine delay segment apply a coarse delay and a fine delay to an external clock signal to generate an internal clock signal. To keep the external and internal clock signals synchronized, the DLL adjusts the fine delay or coarse delay by increasing or decreasing the fine delay or the coarse delay. The coarse delay is adjusted only when the fine delay is at a minimum or maximum delay of the fine delay range and an increase or decrease in delay is needed respectively.

A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

The invention discloses a digital pulse width modulator based on a digital delayed-locked loop (DLL). The digital pulse width modulator comprises: a frequency division circuit, a DLL oscillation loop circuit, a reset signal generation circuit and a PWM output logic circuit. By using inputting a high frequency clock signal fs, the DLL oscillation loop triggers a oscillation loop to perform concussion outputting a 2 channel signal and then the signal is sent to the reset signal generation circuit. The reset signal generation circuit combines the input fs and a duty ratio command signal of mbits so as to generate a pulse signal PWM_clr. Under an effect of post-stage PWM output logic circuit, the PWM signal is generated so as to be taken as the output of the system. The DLL oscillation loop circuit uses a programmable delay unit (PDU) to real-timely track the input signal so that the effect of outputting a good pulse width modulation wave under different process corners and differentworking environments can be achieved. By using the digital pulse width modulator of the invention, areas needed by a chip can be minimized to a larger degree and costs of chip development can be saved.

Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of unit delay elements in the delay line can be selected to produce a desired output signal delay. Phase-mixing of multiple variable delay line outputs achieves finer delay-time adjustments.

The invention discloses a digital delay device, which comprises a delay part, a first control logic circuit and an output clock selection circuit, wherein the delay part comprises a first delay circuit and a second delay circuit, which are used for processing digital signals respectively, and the digital signals are differential signals of each other; the first control logic circuit is used for controlling the first and second delay circuits to output a first clock signal and a second clock signal respectively; and the output clock selection circuit is used for outputting a third clock signal according to the first clock signal and/or the second clock signal. The problem that a great number of delay units of a delay chain are required to cause loud clock jitter noise when a digital delay locked loop is required to have maximum delay time in related technologies is solved, and the effect of lowering the clock jitter noise is achieved.

A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.

A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.

A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a lower power implementation of the clock and data recovery function. An integrated voltage is converted to a digital code by an analog-to-digital converter (ADC), and the digital code is used either directly or after (low frequency) digital signal processing to control a a controllable delay element, such as, a phase rotator, for data edge tracking.