208 results about "Phase splitter" patented technology

A mixing method and mixer structure provide a circuit topology suitable for use in radio receivers, transmitters, tuners, instrumentation systems, telemetry systems, and other systems and devices performing frequency conversion in either homodyne or heterodyne implementations. The inventive mixer may be used for wireless communication devices including radios, cellular telephones, and telemetry systems whether land, sea, airborne, or space based, and whether fixed or mobile. The mixer provides superior intermodulation and harmonic distortion suppression and features excellent conversion loss, noise figure, port match, and port isolation as a result of its circuit topology. The mixer device circuit combines the advantages of series mixing FETs, a triple balanced design using a balanced passive reflection transformer, a precise local oscillator phase splitter, and square wave gate drive having high slew rate signal characteristics to achieve high levels of performance. It is power conservative and offers the advantage of long battery life in portable devices such as portable radios and cellular telephones as it requires only a modest amount of DC and local oscillator drive power, and is useful for operation over at least a multi-decade bandwidth.

A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

A channelized active bandpass filter having only two branches which provide respective frequency-selective feed-forward signal paths. The two signal paths have overlapping frequency response bands such that the combination of the two paths provides a composite filter with a bandpass response. The two branches may be provided with bandpass transfer characteristics of different orders and shapes, such as a second-order response and a fourth-order response. Two-way signal splitting and combining to define the two channels may be performed with in-phase splitters and combiners, for example, or diplexer circuits, each composed of two bandpass filters with different characteristics but overlapping frequency responses and preferably approximately equal center frequencies. Combinations of the two splitting and combining arrangements are also usable.

A wide bandwidth, multi-FET current sharing output stage, MOS audio power amplifier employs multiple feedback loops. An audio input is supplied to a voltage feedback amplifier stage driving a push-pull voltage gain / phase splitter stage. A bias adjustment stage driven from the push-pull voltage gain / phase splitter stage drives a current drive stage. The current drive stage drives an output stage comprising a plurality of paralleled current shared individual MOS output transistors driving an output nodeconnected to a load. Up to three feedback loops are employed. A first voltage feedback loop comprises a voltage feedback stage having an input connected to a voltage divider driven from the first terminal of the load and an output connected to a feedback input node in the voltage feedback amplifier stage. A second voltage feedback loop comprises a voltage feedback stage having an input connected to the first terminal of the load and an output connected to a feedback input node in the push-pull voltage gain / phase splitter stage. A third feedback loop comprises a current feedback stage having an input in series between the output node and the load and an output connected to a feedback input node in the voltage feedback amplifier stage. The current feedback connection works in conjunction with input stage to lower distortion and provide a relatively flat frequency response.

Polar modulators include a phase splitter, a controller, variable current sources, transistor circuits, and a combiner. The phase splitter splits a RF carrier signal into quadrature component signals that are 90 degrees out of phase with each other. The controller generates modulation control signals based on information that is to be transmitted. The variable current sources each generate a variable amplitude current signal based on a different one of the modulation control signals. Each of the transistor circuits amplify a different one of the quadrature component signals with a variable amplification based on the variable amplitude current signal from a different one of the variable current sources to generate an amplitude adjusted quadrature component signal. The combiner combines the amplitude adjusted quadrature component signals from each of the transistor circuits to generate a phase-modulated RF carrier output signal.

Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.

The invention relates to a novel azeotropic distillation technical method and a device, particularly to a technical method and a device using a bulkhead azeotropic distillation column to produce anhydrous isopropanol. The invention enables the separation between isopropanol and water, as well as the recovery of entrainer to be integrated into the same distillation column. The bulkhead azeotropic distillation column refers to a piece of bulkhead (6) which is arranged in the vertical direction inside the conventional distillation column and extended from the upper part of the distillation column to the bottom part of the distillation column; the total height of the bulkhead (6) is less than that of the distillation column; the bottom of the bulkhead is closed; the bulkhead (6) divides the distillation column into three parts: a public distillation segment (1), a dehydration segment (2) and a lateral line distillation segment (3). The isopropanol aqueous solution which needs to be separated enters into the distillation column from the lower part of the public distillation segment (1) and get the high-purity isopropanol from the bottom of the dehydration segment (2); the , ternary azeotrope is steamed out from the top of the distillation column; the steam at the top of the distillation column is condensed through a condenser (5) and then enters into a phase splitter (4) to be divided into light and heavy two-phase liquid; the light phase (entrainer) flows back, while the heavy phase enters into the lower part of the lateral line distillation segment (3) to get the water containing a small amount of isopropanol at the bottom of the lateral line distillation segment (3).

An RFID label with embedded tag is passed through an RFID antenna in a printer system, where the RFID antenna allows a roll of such labels to pass in close proximity to the antenna and still allow each individual RFID tag to be read and / or programmed. The RFID antenna module is formed with a transmission line coupled to an RF phase splitter, where in one embodiment, the transmission line is formed from two parallel conductive strips.

A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

The invention relates to a novel azeotropic distillation process method and a device thereof, in particular to a process method which use a septal azeotropic distillation column (5) to produce absolute alcohol, and a device thereof. The septal azeotropic distillation column (5) is achieved by arranging a septal wall (6) in the azeotropic distillation column in the vertical direction, and the septal wall (6) divides the space of the azeotropic distillation column into three areas with different functions; a public distillation part (1), a dehydration part (2) and a side stripper part (3). The alcohol solution to be separated is filled to the azeotropic distillation column from the upper part of the dehydration part (2), and the absolute alcohol is obtained at the bottom of the dehydration part (2); ternary azeotrope is steamed out of the top of the column, and condensed by a condenser (7) and then splitted into light phase solution and heavy phase solution in a phase splitter; the light phase solution (entrainer) reflows and the heavy phase solution is the feed stock in the side stripper part (3), and little water containing alcohol is obtained at the bottom of the side stripper part (3). The device and the process method of the invention can produce the absolute alcohol, and can simplify the process, reduce the energy consumption and the cost of the divices.

The invention discloses a process for preparing furfural by using agricultural by-products of high and crude fiber plants. The process includes the steps of 1) conducting pretreatment of raw materials; 2) hydrolyzing pretreated raw materials in a hydrolyzing tank, and using an acid catalyst formed by mixing sulfuric acid and phosphoric acid during the hydrolytic process; 3) introducing high-temperature steam into the hydrolyzing tank, heating up the hydrolyzing tank, and conducting gap stripping for hydrolysis products of furfural; and 4) feeding gas stripped furfural to into a furfural phase splitter to obtain coarse furfural and furfural residues. According to the process, the acid catalyst combining the sulfuric acid and the phosphoric acid is used for hydrolyzing the raw materials, and the hydrolytic process is assisted by ultrasonic treatment simultaneously, so that the productivity of the furfural is improved, the residue amount of the sulfuric acid is a little, the production of sulfur oxides in the subsequent activating process of furfural residues is reduced, and the environmental pollution is reduced. Besides, the invention also provides a process for producing activated carbon adsorbents by using the furfural residues. The process includes the steps of drying the furfural residues, screening, roasting, hardening activating and steam curing, the obtained activated carbon specific surface is large, the iodine value is high and the adsorption capacity is high.

A power factor correction controller simultaneously controls several power converters to be operated at a critical conduction mode to improve the overall conversion efficiency and conversion power of the power factor corrector. The controller includes a primary power converter control circuit for feeding back an input voltage signal, an output voltage signal and a primary current signal, and outputting a primary gate control signal for controlling a primary power switch; at least one secondary power converter control circuit for receiving the primary gate control signal and outputting a secondary gate control signal for controlling a secondary power switch; and a phase splitter circuit for receiving the primary gate control signal to control a gate output driving circuit, so that the gate output driving circuit outputs the secondary gate control signal.

A multi-phase separation apparatus shapes fluid flow in a flow shaping line preferably shaped to have a plurality of loops with consecutively decreasing diameters. Shaping the two-phase flow drives the heavier, denser fluids to the outside wall of the flow shaping line and allows the lighter, less dense fluids such as gas to occupy the inner wall of the flow shaping line. With the gas positioned on the inner wall, an exit port on the inner wall permits a majority, if not all, of the gas, along with a minimal amount of liquid, to be diverted to a conventional gas-liquid separator at a flow rate much lower than the total flow rate within the flow shaping line. The remaining liquid flow in the flow shaping line is subsequently introduced into an adjustable phase splitter to separate different liquid components from one another.

A wide bandwidth, multi-FET current sharing output stage, MOS audio power amplifier employs multiple feedback loops. An audio input is supplied to a voltage feedback amplifier stage driving a push-pull voltage gain / phase splitter stage. A bias adjustment stage driven from the push-pull voltage gain / phase splitter stage drives a current drive stage. The current drive stage drives an output stage comprising a plurality of paralleled current shared individual MOS output transistors driving an output nodeconnected to a load. Up to three feedback loops are employed. A first voltage feedback loop comprises a voltage feedback stage having an input connected to a voltage divider driven from the first terminal of the load and an output connected to a feedback input node in the voltage feedback amplifier stage. A second voltage feedback loop comprises a voltage feedback stage having an input connected to the first terminal of the load and an output connected to a feedback input node in the push-pull voltage gain / phase splitter stage. A third feedback loop comprises a current feedback stage having an input in series between the output node and the load and an output connected to a feedback input node in the voltage feedback amplifier stage. The current feedback connection works in conjunction with input stage to lower distortion and provide a relatively flat frequency response.

An embodiment of the invention is a predistortion approach to linearize a power amplifier without frequency conversion of the RF signals by using envelope and phase detectors to detect the error to be corrected, and then one or more analog multiplier(s) and a DSP-based processor. For the analog embodiment, the inherent nature of the analog circuitries allows digital predistortion processing structured directly at the RF band, and enables a single power amplifier to support multi-modulation schemes, multi-carriers and multi-channels. As a result, the predistortion architecture is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems. The wireless system performance can be improved and upgraded just by using the new PA module rather than change or rebuild new subsystem in existing base station. The analog embodiment can also mix and match its analog multipliers with other analog components such as phase splitters, phase shifters, attenuators, filters, couplers, mixers, low-noise amplifiers, buffers, envelope detectors, and etc., to provide additional features.

A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an output clock; a phase splitter for generating a rising and a falling clocks by phase-splitting the output clock; a DCC pumping unit for generating a rising and a falling duty ratio correction signals according to a reset signal; a voltage comparing unit for generating counting increase and decrease signals according to a result of comparing the rising and the falling duty ratio correction signals in response to a comparison control signal; a comparison control unit for generating the comparison control signal and the reset signal; and a counter for increasing / decreasing a value of the count signal according to the counting increase and decrease signals.

Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.

An odd number factor frequency divider which generates a final output signal having a duty ratio of 1 / 2 is formed of a plurality of cascade-connected MSD-FFs (master-slave D-type flip-flops), operating from a common clock signal, with a single NOR gate being used to derive a signal expressing the negated logic sum of the respective Q-terminal logic outputs from the master D-type latch and the slave D-type latch which constitute the final-stage MSD-FF of the plurality of cascade-connected MSD-FFs, with that output signal from the NOR gate being applied to the D input terminal of the first-stage MSD-FF, while also being supplied to an output terminal as the final output signal from the frequency divider. Since a minimum number of circuit elements are employed, the overall circuit scale can be small, and current consumption low.

The invention provides a carbon dioxide (CO2) capturing system applicable for a phase change absorbent. The system comprises an absorption tower, a phase splitter, a dense phase pump, at least one stage of an interstage separator, at least one stage of an interstage cooler, a mixer, a rich solution pump, and a desorption tower, wherein the absorption tower comprises a tower cavity; the part of thetower cavity between a first inlet of the absorption tower and a second inlet of the absorption tower is divided into a plurality of stages, and a barren solution containing the phase change absorbent is stored in each stage of the tower cavity; the phase change absorbent contains nanoparticles; and each stage of the interstage separator communicates with a corresponding stage outlet of the absorption tower. The CO2 capturing system applicable for the phase change absorbent has the advantages that the nanoparticles achieve the function of enhancing gas-liquid mass transfer, that is, the nanoparticles can improve the heat transfer rate of the phase change absorbent in CO2 in captured exhaust gas, and accelerate the reaction between the phase change absorbent in the CO2 in the captured exhaust gas and the CO2, so that the CO2 absorption capacity and the CO2 capturing rate can be improved; and moreover, the solution treatment amount during desorption is reduced, so that the energy consumption is lowered.

A wide bandwidth, multi-FET current sharing output stage, MOS audio power amplifier employs multiple feedback loops. An audio input is supplied to a voltage feedback amplifier stage driving a push-pull voltage gain / phase splitter stage. A bias adjustment stage driven from the push-pull voltage gain / phase splitter stage drives a current drive stage. The current drive stage drives an output stage comprising a plurality of paralleled current shared individual MOS output transistors driving an output node connected to a load. Up to three feedback loops are employed. A first voltage feedback loop comprises a voltage feedback stage having an input connected to a voltage divider driven from the first terminal of the load and an output connected to a feedback input node in the voltage feedback amplifier stage. A second voltage feedback loop comprises a voltage feedback stage having an input connected to the first terminal of the load and an output connected to a feedback input node in the push-pull voltage gain / phase splitter stage. A third feedback loop comprises a current feedback stage having an input in series between the output node and the load and an output connected to a feedback input node in the voltage feedback amplifier stage. The current feedback connection works in conjunction with input stage to lower distortion and provide a relatively flat frequency response.

The invention relates to a method and a device for treating and recovering low-concentration acetic acid wastewater generated in a pharmaceutical factory. Equipment of the whole technical flow mainly comprises a two-stage extraction tower, a stripping tower, an acetic acid treating column and corresponding auxiliary equipment thereof. The method comprises the following steps of: adding the acetic acid wastewater from the top of the two-stage extraction tower, and adding an extracting agent from the bottom of a primary extraction tower at a certain flow velocity to pass through the two-stage extraction tower; making the acetic acid-enriched extraction raffinate obtained by two-stage extraction enter the acetic acid treating column for separation, and obtaining high-purity acetic acid at the bottom of the tower, wherein the extracting agent recovered on the top of the tower can be added into an extracting agent system for recycling; making the aqueous solution which is subjected to two-stage extraction and contains a small amount of extracting agent enter the stripping tower, directly discharging the treated wastewater from the bottom of the tower, and recycling an oil phase of a phase splitter, namely the extracting agent on the top of the tower. Due to the technical treatment, the acetic acid content in the wastewater is less than 100ppm, the purity of the acetic acid is over 99.0 weight percent, and the recovery rate is over 98.0 percent.

Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.