1434 results about "Subtractor" patented technology

A power control circuit is provided containing a switch array, which includes segmented switches, a flying capacitor, an output voltage terminal, a feedback loop, and a digital voltage regulator block. The digital voltage regulator block includes an A / D converter, an encoder, an add-subtractor, and a gate logic. These power control circuits do not include pass transistors. A method is also provided, where the charge pumps of the power control circuit are operated in two-phase cycles including a charging phase and a pumping phase. The power control circuit is controlled in both of these phases, thereby reducing the ripple of the output voltage.

A frequency upconverter using mixers operating on one or more signals and inverted versions thereof and a subtractor, such as a balun, for subtractively combining the mixer outputs to produce an upconverted signal.

An accurate target detection system. The system includes a sensor (22) that receives electromagnetic signals and provides electrical signals in response thereto. A non-uniformity correction circuit (28, 38, 52) corrects non-uniformities in the sensor (22) based on the electrical signals and provides calibrated electrical signals in response thereto. A third circuit (30, 32, 34, 38, 42, 44, 52) determines if a target signal is present within the calibrated electrical signals and provides a target detection signal in response thereto. A fourth circuit (38, 40, 48) selectively activates or deactivates the non-uniformity correction circuit (28, 38, 52) based on the target detection signal. In a specific embodiment, the sensor (22) is an array of electromagnetic energy detectors (22), each detector providing an electrical detector output signal The non-uniformity correction circuit (28, 38, and 52) includes circuit for compensating for gain, background, and noise non-uniformities (28, 38, and 52) in the electromagnetic energy detectors. The non-uniformity correction circuit (28, 38, and 52) includes a detector gain term memory (28) for storing detector gain compensation values. The detector gain compensation values are normalized by noise estimates unique to each of the detectors. The third circuit (30, 32, 34, 38, 42, 44, and 52) includes a signal enhancement circuit for reducing noise (34, 42) in the calibrated electrical signals. The third circuit (30, 32, 34, 38, 42, 44, and 52) includes a noise estimation circuit (32, 38) that estimates noise in each of the detector output signals and provides noise estimates in response thereto. The noise estimation circuit (32, 38) further includes a noise estimator circuit (38) and a recursive background estimator (32). The third circuit (30, 32, 34, 38, 42, 44, 52) further includes a subtractor (30) for subtracting background from the calibrated electrical signals and providing background subtracted signals in response thereto. The signal enhancement circuit (34, 42) includes a frame integrator circuit for adding frames of image data (34), each frame containing data corresponding to the background subtracted signals and providing summed frames in response thereto. The third circuit (30, 32, 34, 38, 42, 44, 52) includes a first threshold circuit (44) for comparing the filtered signal to a first threshold and a second threshold and providing a threshold exceedance signal if the filtered signal is between the first threshold and the second threshold.

Systems and methods for performance improvements in digital switching amplifiers using simulation-based feedback. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a simulator configured to model processing of audio signals by the plant. The outputs of the plant and the simulator are provided to a subtractor, the output of which is then added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal for input to the subtractor. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

To provide a video coding method with which prediction efficiency and coding efficiency can be optimized and a video coding device. A video coding device (100) codes video data by performing a motion compensation with decimal pixel accuracy by using an adaptive interpolation filter for calculating a pixel value of a decimal pixel that performs interpolation between integer pixels configuring an input image included in the video data. The video coding device (100) comprises a motion compensation prediction unit (160) which sets a filter characteristic of the adaptive interpolation filter for each predetermined process unit, decides a plurality of filter coefficients of the adaptive interpolation filter having the set filter characteristic for each location of the decimal pixels that are relative to the integer pixel, and performs the motion compensation with the decimal pixel accuracy by applying the adaptive interpolation filter having the plurality of decided filter coefficients to the input image, a subtractor (110) which generates a prediction error by performing a subtraction between the prediction image generated by the motion compensation and the input image and an entropy coding unit (190) which codes the prediction error.