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473results about How to "High error rate" patented technology

Non-Volatile Memory And Method With Accelerated Post-Write Read To Manage Errors

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.
Owner:SANDISK TECH LLC

Novel peptides and combination of peptides for use in immunotherapy against small cell lung cancer and other cancers

The present invention relates to peptides, proteins, nucleic acids and cells for use in immunotherapeutic methods. In particular, the present invention relates to the immunotherapy of cancer. The present invention furthermore relates to tumor-associated T-cell peptide epitopes, alone or in combination with other tumor-associated peptides that can for example serve as active pharmaceutical ingredients of vaccine compositions that stimulate anti-tumor immune responses, or to stimulate T cells ex vivo and transfer into patients. Peptides bound to molecules of the major histocompatibility complex (MHC), or peptides as such, can also be targets of antibodies, soluble T-cell receptors, and other binding molecules.
Owner:IMMATICS BIOTECHNOLOGIES GMBH

Error recovery within processing stages of an integrated circuit

An integrated circuit includes a plurality of processing stages each including processing logic 1014 , a non-delayed signal-capture element 1016 , a delayed signal-capture element 1018 and a comparator 1024 . The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014 . An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024 . The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
Owner:ARM LTD +1
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