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354results about How to "Small range" patented technology

Modular multiplicative data rate modem and method of operation

A high speed modem is provided which targets the use of a selectable, desirable portion of the total available bandwidth of a channel for achieving a data rate which nevertheless far exceeds that of conventional voice-band modems. In a preferred embodiment, the invention is implemented in an Asymmetric Digital Subscriber Loop (ADSL), and the nominal data rate is achieved using an analog front end (AFE) with subband filtering which causes an upstream transceiver to use only a selected number of available sub-channels for downstream data transmission and allows slower sampling rate for the AFE. The data rate of the modem is increased in a multiplicative fashion through modular expansion of a bank of AFEs to increase the number of transmitted downstream sub-channels.
Owner:REALTEK SEMICON CORP +1

xDSL DMT modem using sub-channel selection to achieve scaleable data rate based on available signal processing resources

A high speed modem is provided which uses a selectable, desirable portion of the total available bandwidth of a transmission channel. In a preferred embodiment, the invention is incorporated in a dedicated hardware circuit which is connected on one end to a data processor and on the other end to an upstream transceiver through a channel supporting an Asymmetric Digital Subscriber Loop (ADSL) standard. The achievable target data rate of the modem is based on the capabilities of an analog front end (AFE) used in the modem, and a signal processor within the dedicated hardware. In particular, the modem AFE contains subband filtering which causes an upstream transceiver to use only a selected number of available sub-channels for downstream data transmission. The data rate of the modem is increased by upgrading the AFE or the signal processor in order to increase the number of processable transmitted downstream sub-channels.
Owner:ITE TECH INC +1

Amplitude error de-glitching circuit and method of operating

A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The RF power amplifier system may reduce the corrective action of the amplitude loop during periods of relatively rapid changes in amplitude, and thus distortion can be further reduced.
Owner:QUANTANCE

Hierarchical target allocation method for multiple unmanned aerial vehicle formations

The invention discloses a hierarchical target allocation method for multiple unmanned aerial vehicle formations. The method is characterized by comprising the following steps of 1, clustering a plurality of ground targets to form a plurality of target clusters according to the number of the unmanned aerial vehicle formations; 2, regulating the obtained target clusters to keep the number of the ground targets in each target cluster consistent; 3, allocating the target clusters to the unmanned aerial vehicle formations in a one-to-one correspondence way by using an inter-unmanned aerial vehicle formation target allocation model and an inter-unmanned aerial vehicle formation target allocation algorithm; 4, allocating the ground targets to each unmanned aerial vehicle in the unmanned aerial vehicle formations by using an intra-unmanned aerial vehicle formation target allocation model and an intra-unmanned aerial vehicle formation target allocation algorithm. According to the method, the target allocation efficiency can be improved, and the problem of excessively long calculation time during large-scale target allocation for the multiple unmanned aerial vehicle formations can be effectively solved, so that the requirements of an application scenario such as a battlefield with a higher requirement on real-time performance are met.
Owner:HEFEI UNIV OF TECH

Construction method of large-span subway station main body by using arched cover method and station main body structure

The invention discloses a construction method of a large-span subway station main body by using an arched cover method and a station main body structure. The construction method comprises the following steps: 1. making first-phase preparations; 2. excavating main body pilot tunnels at the left side and the right side, and carrying out primary support and top beam construction; 3. excavating a middle-part main body pilot tunnel, carrying out primary support and arch buckling construction, and refilling the earthwork; 4. carrying out earthwork excavation on a main body structure in the station, and prestressing force anchor cable construction; 5. carrying out secondary lining construction on the main body structure in the station; and 6. carrying out secondary lining and arch buckling construction on the station main body. The station main body structure comprises the main body structure in the station, a central post, a central plate and a main body arch part, wherein, the main body arch part comprises a middle arch fragment and two side arch fragments respectively arranged in the two side main body pilot tunnels formed by excavation in advance; and the main body arch part comprises a primary support system and a station main body arch buckling secondary lining structure from the outside to the inside. The station main body structure provided by the invention has reasonable design, simple construction steps, convenience in realization, small construction difficulty and rapid construction speed; the subway station formed by the construction method has a stable structure and a good use effect.
Owner:CHINA RAILWAY FIRST GRP CO LTD +1

Schottky barrier quantum well resonant tunneling transistor

InactiveUS20100102298A1High speedReduce series resistanceTransistorSolid-state devicesQuantum wellSchottky barrier
A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 Å. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.
Owner:WU KOUCHENG
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