A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device comprises a register to store a value which is representative of a
delay time after which the memory device responds to a read request and
clock receiver circuitry to receive first and second external
clock signals. The memory device also includes an output driver(s) to output data on a
bus, in response to a read request and in accordance with the
delay time, wherein a first portion of the data is output synchronously with respect to the first external
clock signal and a second portion of the data is output synchronously with respect to the second external
clock signal. The memory device may include a
delay locked loop to generate internal
clock signal(s) using the external
clock signal(s). The output drivers output data on the
bus in response to the internal clock
signal(s). The memory device may include input
receiver circuitry, coupled to the
bus, the receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock
signal.