387 results about "Lock time" patented technology

Disclosed is a method for automatically locking a mobile terminal having functions, such as incoming and outgoing calls. The method includes the steps of setting an auto-lock time period to restrict the use of one or more predetermined functions; activating an auto-lock mode to restrict the use of the predetermined functions during the auto-lock time period; and inactivating the auto-lock mode after the auto-lock time period. The auto-lock mode for automatically locking functions of the mobile terminal can be set to be activated only during specified time or during all other times of the day according to the spatial and temporal patterns of the user's daily routine.

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.

A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.

The invention provides a ball joint locking method and a locking device designed according to the method. A ball head of a ball joint is sleeved with a connecting sleeve which can be movably locked with the ball head or be in a release state with the ball head. An abutting assembly connected with a hydraulic system is arranged in a position corresponding to a matching position of the ball head and the connecting sleeve at locking time. Under the action of pressure oil provided by the hydraulic system, the abutting assembly is forced to instantly press the outer surface of the ball head and enables the ball head to abut against the position matched with the connecting sleeve at the same time, so that the abutting assembly and the connecting sleeve lock the ball head in a multipoint mode. When pressure is released, the abutting assembly and the connecting sleeve can restore to original positions automatically, so that the locking state and the release state of the ball joint can be switched quickly. According to the ball joint locking method and the locking device, the characteristics that the hydraulic system is small in inertia and quick in response are fully utilized, so that that the device have the advantages of being simple in structure, reliable in locking, and good in effect, and can ensure rigid connection and bear certain load moment at the same time. Moreover, locking devices can be connected in series through the same oil path for utilization in one product.

In one set of embodiments, the invention comprises a system and method for automatically trimming the center frequency of a VCO in a PLL. The trimming may be performed by a digitally controlled trimming circuit, which may be operated to modify a gain of the VCO and may be used as part of a clock recovery architecture or as part of a high-end PLL. It may also be used by itself in low-end PLLs. In one embodiment, a second loop based solely on the frequency difference between a reference frequency and a divided output frequency of the VCO is introduced into the PLL loop. This frequency loop may be optimized by the inclusion of a gain control stage, which may lower the locking time. A control module may also be introduced to delay the deployment of the phase detector until the frequency loop has fully converged, that is until trimming has been completed, thus preventing the two loops from interfering with each other and compromising each other's performance.

A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.

The invention discloses a focusing locking method and system for video shooting. The method comprises steps as follows: focusing is performed according to a preset focusing mode in a preview mode of video shooting, focusing locking is performed after focusing success, the focusing locking state is kept within a preset focusing locking time range, after the focusing locking time is up, detection of the angular velocity of a gyroscope and information identification of a preview image are performed, whether unlocking is performed or not is judged according to the change degree of the angular velocity of the gyroscope or the change degree of front and back frames of the preview image, the current focusing locking state is judged when video shooting is started, a camera hardware motor is informed of keeping of the focusing locking state or locking in a designated position for shooting according to the current focusing locking state, and the locking state of the camera hardware motor is kept in the video shooting process until focusing retriggering or shooting completion. Therefore, the problem of recording focusing displacement caused by repeated focusing is effectively solved, and the video capture effect is improved.

A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.

A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

A register controlled delay locked loop includes a clock generation unit which receives an external clock signal for generating a source clock signal by buffering the external clock signal and for generating a delay monitoring clock signal and a reference clock signal by diving the source clock signal by a natural number; a delay line control unit which receives the reference clock signal and a feed-backed clock signal for generating a normal shift control signal and an acceleration shift control signal based on a result of a comparison between phases of the reference clock signal and the feed-backed clock signal; a delay line unit which receives the source clock signal for generating a delay locked clock signal by delaying the source clock signal according to a delay amount of the delay line unit determined by the normal shift control signal and the acceleration shift control signal; and a delay model unit for estimating a delay amount generated while the external clock signal is passed to a data output pin to generate the feed-backed clock signal, wherein an absolute delay amount based on the acceleration shift control signal is larger than that based on the normal shift control signal.

The invention relates to a configurable phase discriminator for a time-delay locking ring, which comprises a configurable SRAM, an integral resetting module, an advanced-lagged signal generating module and a fine adjusting range identification signal generating module. Data in the embedded configurable SRAM is changed and different phase discriminating precisions are set according to different application requirements, so as to realize the controllability of fine and rough adjusting; meanwhile, as the embedded configurable SRAM controls different starting moments of fine adjusting, the structure of hardware does not need to be changed in the using process and the locking time of a loop circuit can be adjusted only by changing a code stream in the SRAM according to the requirements. In addition, the advanced-lagged signal generating module which is composed of two D triggers and three RS triggers is used for sampling and outputting two input clock signals and judging whether the two input clock signals are advanced or lagged; the fine adjusting range identification signal generating module which is composed of a nand gate and two pulse generating circuits is used not only for judging whether the phase difference of the two clocks reaches the set fine adjusting range, but also for controlling the starting time of fine adjusting by controlling the pulse generating width.

A bus-repeater for coupling at least one first bus with a second bus, by way of which data may be transmitted in the form of serial digital signal pulse sequences and including at least one first and a second transmit-receive means, with which the first and, respectively, the second bus may be coupled and by way of which the bus-repeater may transmit signal pulse sequences, received via the first bus on the second bus, and vice versa. In accordance with the invention the bus-repeater comprises locking means, which during transmission of a signal pulse received from the first bus to the second bus lock transmission by the bus-repeater of signal pulses, received from the second bus, via the first bus for a transmission locking time and vice versa.