1220 results about "Clock recovery" patented technology

A method and system for initializing a coherent optical receiver. Upon detection of an optical signal, a multi-bit digital sample stream of the optical signal is digitally processed to initialize each one of a plurality of adaptive control blocks of the coherent optical receiver. The adaptive control blocks include at least a dispersion compensation block and a clock recovery block. The dispersion compensation block is initialized before initializing the clock recovery block.

An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information. Finally, the isolation system may include a pulse transformer to accommodate ADSL circuitry, whereby power is transmitted through the pulse transformer.

A partial response maximum likelihood (PRML) data detecting in a magnetic recording storage device is carried out with a preliminary measuring of write-read channel responses to all nonzero binary combinations of a given length. Decoding of the user data is performed according to a Viterbi algorithm, where the previously measured responses are used as expected samples for branch metric calculations. The measurement of the write-read channel responses and the decoding of the user data are fulfilled by a self-adjusting PRML receiver that contains a controllable clock recovery, a responses accumulator and an adjustable Viterbi detector. The controllable clock recovery produces a set of read-back signal samples containing exactly one sample per bit with or without phase error correction. The responses accumulator calculates averaged responses of the write-read channel. The adjustable Viterbi detector reconstructs the user data that were written to the disk.

A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, selecting one of the multiphase signals based on synchronization states identifying which of the multiphase clock signals is most closely aligned with the data stream, and sampling the data stream using the selected multiphase signal to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. The selecting step may include the determination of whether the multiphase clock signals are either early or late with respect to the data stream, particularly using D-type flip-flops. The synchronization states are used to define which of the rising edges of the multiphase clock signals is most closely aligned with an edge of the data stream. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals. An error signal is created using the multiphase clock signals and the data stream which is applied to a charge pump, and the multiphase clock signals are corrected using a control voltage output of the charge pump.

A network interface for recovering timing information over packet networks has line card at the edge of a local network and a timing card separate from the line card. A physical interface time-stamps incoming timing packets based on smoothed recovered clock signals. A clock recovery module on the line card generates timing signals from the time-stamped incoming timing packets. A first phase locked generates raw clock signals from the timing signals. A second phase locked loop on the timing card generates the smoothed clock signals from said raw clock signals and applies them to the clock recovery module on the line card.