74 results about "Packet delay variation" patented technology

This invention relates to methods and devices for time synchronization. The invention has particular application in the alignment of slave clocks to a master clock and in dealing with packet delay variation and dynamic asymmetries in the network links between them. In embodiments of the invention, the slave clock uses the peer link delay and residence times measured by peer-to-peer transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

A method and system for simulating packet delay variation (PDV) is disclosed. The delay-step method for simulating PDV determines a delay for each packet is a stream of packets generated at a regular interval. Delay target values are randomly selected based on a statistical distribution, such as a Gamma distribution, which models a desired PDV. Delay-steps are determined for each packet based on the delay target values. The delay-steps can be fixed or variable sized steps which are used to adjust the delay of sequential packets. Each of the packets is then transmitted with the delay determined for that packet.

A method for scheduling packets from a plurality of radio bearers by a scheduler of a first layer includes calculating a virtual scheduling time for the radio bearers by using a packet delay variation of the radio bearers, and transmitting the packet of the radio bearer having the greatest virtual scheduling time from among the plurality of radio bearers to a second layer.

Embodiments of the invention provide a method and an apparatus for simulating Packet Delay Variation (PDV) in a current network. The method includes: a first clock packet including a first time is transmitted, with the period of t, to a slave clock device, so that the slave clock device returns a second clock packet after receiving the first clock packet, wherein the first time is a difference value between the time for transmitting the first clock packet and a first network delay in the current network, the time when the slave clock device receives the first clock packet is a second time, and the time when the slave clock device transmits the second clock packet is a third time; after the second clock packet is received, a fourth time is transmitted to the slave clock device, so that theslave clock device adjusts, according to the first time, the second time, the third time and the fourth time, the slave clock to synchronize with a master clock, wherein the fourth time is a sum of the time when the second clock packet is received and a second network delay in the current network. The embodiments of the invention achieve simulating the PDV procedure in the current network, can perform a PDV test for the current network in a simulation environment, and achieve the feasibility validation for clock algorithms in the current network.