Method and apparatus for simulating packet delay variation in current network

Abstract

Embodiments of the invention provide a method and an apparatus for simulating Packet Delay Variation (PDV) in a current network. The method includes: a first clock packet including a first time is transmitted, with the period of t, to a slave clock device, so that the slave clock device returns a second clock packet after receiving the first clock packet, wherein the first time is a difference value between the time for transmitting the first clock packet and a first network delay in the current network, the time when the slave clock device receives the first clock packet is a second time, and the time when the slave clock device transmits the second clock packet is a third time; after the second clock packet is received, a fourth time is transmitted to the slave clock device, so that theslave clock device adjusts, according to the first time, the second time, the third time and the fourth time, the slave clock to synchronize with a master clock, wherein the fourth time is a sum of the time when the second clock packet is received and a second network delay in the current network. The embodiments of the invention achieve simulating the PDV procedure in the current network, can perform a PDV test for the current network in a simulation environment, and achieve the feasibility validation for clock algorithms in the current network.

Description

technical field [0001] The embodiment of the present invention relates to the field of communication technologies, and in particular to a method and device for simulating packet delay jitter in an existing network. Background technique [0002] With the development of IP network, most communication networks have realized IP transmission now. Since the IP network is an asynchronous network, the clock cannot be obtained through the physical link of the IP network. At present, the clock synchronization of IP clock is relatively mature, but when the intermediate network equipment does not support IEEE (Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers) 1588, it is necessary to know the IP packet delay jitter (Packet DelayVariation, hereinafter referred to as: PDV) feature can well realize IP clock synchronization. Among them, PDV represents the delay and jitter from the time w...

AI Technical Summary

Problems solved by technology

However, due to the increasingly complex transmission network of the current network, the cost of building various transmission networks in the laboratory is relatively high, and for complex transmission networks, the environment built in the laboratory may not be able to simulate the environment of the current network, resulting in inaccurate test data. precise

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