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Method and devices for time and frequency synchronization using a phase locked loop

A digital phase-locked loop, time technology, used in synchronization devices, automatic power control, multiplexing communication, etc., can solve problems such as clock signal deterioration

Active Publication Date: 2016-05-25
KHALIFA UNIV OF SCI & TECH +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The processing and buffering of packets in network devices (switches, routers, etc.) introduces variations in the time delay of packets traveling through the packet network 2, which often results in the degradation of the transferred clock signal

Method used

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  • Method and devices for time and frequency synchronization using a phase locked loop
  • Method and devices for time and frequency synchronization using a phase locked loop
  • Method and devices for time and frequency synchronization using a phase locked loop

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Embodiment Construction

[0080] Development of basic clock models and measurement and processing models

[0081] Consider the time server (master) clock S and the time client (slave) clock C separately. The difference or offset of clock C relative to S at time t≥0 is θ(t)=(S(t)−C(t)). t is used to indicate real or reference (ideal) time. Frequency is the rate at which a clock advances, and the frequency of S at time t is s'(t). Skew α is defined as the normalized frequency difference between a clock and another clock. Generalized clock skew and skew equations can then be defined for synchronization problems. Assuming at any particular moment, an instantaneous diagram of the relationship between a master (server) clock with timeline S(t) and a slave (client) clock with timeline C(t) can be given by Figure 5 is described by the known simple skewed clock model shown, and is described by the following equation,

[0082] S(t)=(1+α)C(t)+θ, (1)

[0083] Among them, the normalized α is a very small quan...

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Abstract

This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

Description

technical field [0001] The present invention relates to methods and devices for time and frequency synchronization. In particular, but not exclusively, it relates to time and frequency synchronization using phase locked loops over packet networks using eg IEEE1588 Precision Time Protocol (PTP). Background technique [0002] Mobile networks fall into two categories: Frequency Division Duplex (FDD), which transmits / receives using two separate frequency bands, and Time Division Duplex (TDD), which transmits and receives on a single frequency band. LTE-TDD, WiMAXTDD, CDMA networks (common in North America), TD-CDMA and TD-SCDMA (in addition to frequency synchronization) require time synchronization, while LTE-FDD, GSM (Global System for Mobile Communications), W-CDMA and others Wireless technology requires only frequency synchronization. Even with the use of LTE-FDD, new LTE mobile services such as network MIMO and location-based services will require precise time synchronizat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/06H04L7/033H03L7/099
CPCH03L7/0994H03L2207/50H04J3/0667H04L7/0331
Inventor J·阿维亚
Owner KHALIFA UNIV OF SCI & TECH
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