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7767results about "Pulse shaping" patented technology

Apparatus and method for controlling a master/slave system via master device synchronization

A method of operating a master / slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.
Owner:RAMBUS INC

Wireless communication system and method using multiple antennas

A wireless communication system, and method using multiple antennas, includes a base station that applies predetermined weight vectors to multi-user signals and transmits the multi-user signals through a plurality of transmission antennas, and a plurality of mobile stations that receive and process the multi-user signals, wherein each mobile station includes a signal reception unit that processes the multi-user signals, and a feedback signal generation unit that estimates channel characteristics, over which the multi-user signals have been transmitted, from the multi-user signals, classifies a plurality of weight vectors to be applied to the estimated channel characteristics into a plurality of sets such that vectors orthogonal to one another are classified into a single set, selects a set maximizing a transmission capacity from among the classified sets, and feeds back weight indexes of weight vectors included in the selected set and weighted channel information to the base station.
Owner:NOKIA SOLUTIONS & NETWORKS OY

System and method for distributed input distributed output wireless communications

A system and method are described for compensating for frequency and phase offsets in a multiple antenna system (MAS) with multi-user (MU) transmissions (“MU-MAS”). For example, a method according to one embodiment of the invention comprises: transmitting a training signal from each antenna of a base station to one or each of a plurality of wireless client devices, one or each of the client devices analyzing each training signal to generate frequency offset compensation data, and receiving the frequency offset compensation data at the base station; computing MU-MAS precoder weights based on the frequency offset compensation data to pre-cancel the frequency offset at the transmitter; precoding training signal using the MU-MAS precoder weights to generate precoded training signals for each antenna of the base station; transmitting the precoded training signal from each antenna of a base station to each of a plurality of wireless client devices, each of the client devices analyzing each training signal to generate channel characterization data, and receiving the channel characterization data at the base station; computing a plurality of MU-MAS precoder weights based on the channel characterization data, the MU-MAS precoder weights calculated to pre-cancel frequency and phase offset and/or inter-user interference; precoding data using the MU-MAS precoder weights to generate precoded data signals for each antenna of the base station; and transmitting the precoded data signals through each antenna of the base station to each respective client device.
Owner:REARDEN

Delay locked loop circuit with duty cycle correction function

A delay locked loop (DLL) circuit having a structure in which a method of performing duty cycle correction (DCC) using two DLLs and an intermediate phase composer and a method of performing DCC by forming a closed loop using a negative feedback are combined with each other is provided. The DLL circuit includes a first DLL for receiving an external clock signal and generating a first clock signal and a second DLL for receiving an external clock signal and generating a second clock signal. The first clock signal and the second clock signal are synchronized with an external clock signal. The DLL circuit further includes an intermediate phase generation circuit for receiving the first and second clock signals and generating an intermediate phase clock signal and a DCC loop for receiving the intermediate phase clock signal and generating an output clock signal. The intermediate phase clock signal has an intermediate phase between the phases of the first and second clock signals. The output clock signal is generated through correction of the duty cycle of the intermediate phase clock signal using a value obtained by integrating the output clock signal.
Owner:SK HYNIX INC

Blind adaptive filter for narrowband interference cancellation

The present invention relates to a blind adaptive filter for narrowband interference cancellation, which includes an adaptive filter, a delay unit coupled to the adaptive filter for generating a delayed signal with a predetermined delay length from the output signal of the adaptive filter, and an error calculation unit coupled to the adaptive filter and the delay unit. The error calculation unit compares the output signal from the adaptive filter and the delayed signal from the delay unit to extract error information, and feedback the first error information to the adaptive filter. The first error information is formed of a transfer function including a number of coefficients, and used to adjust the adaptive filter and remove interference in the next input signal. The disclosed technique is also applicable in wideband receivers, as well as resisting multiple strong narrowband interferences having a frequency sweep rate of tens of milliseconds.
Owner:MONTAGE TECHNOLOGY CO LTD

Noise-reducing arrangement and method for signal processing

A communication system uses analog and digital circuits along the same data path in a manner that permits the analog circuitry to avoid adverse affects caused by the digital circuitry. Consistent with one embodiment directed to a signal processing system that detects faint incoming signals, the analog and digital circuits are implemented on a single piece of silicon. In such signal processing systems, noise generated by digital processing blocks can degrade the performance of sensitive analog portions. The effective noise is reduced by causing the analog and digital portions of the system to function during separate time intervals. The noise-generating portions of the system may then be turned off during a first data-communication interval while the analog block operates. The data acquired during this period is stored for subsequent processing by the digital portion during a second shorter data-communication interval. Other aspects are applicable to reception arrangements in which part of the incoming signal may be disregarded without significant degradation in performance of the rest of the system, and other aspects are directed to transmission arrangements in which the inverse of the above reception arrangement is used.
Owner:THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIV
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