2830results about How to "Reduce jitter" patented technology

A virtual computer monitor is described which enables instantaneous and intuitive visual access to large amounts of visual data by providing the user with a large display projected virtually in front of the user. The user wears a head-mounted display containing a head-tracker, which together allow the user to position an instantaneous viewport provided by the head-mounted display at any position within the large virtual display by turning to look in the desired direction. The instantaneous viewport further includes a mouse pointer, which may be positioned by turning the user's head, and which may be further positioned using a mouse or analogous control device. A particular advantage of the virtual computer monitor is intuitive access to enlarged computer output for visually-impaired individuals.

A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

A clock control circuit which includes a frequency multiplying interpolator for generating and outputting multiphase clocks by frequency multiplying an input clock; a switch for outputting two of the multiphase clocks input thereto from the frequency multiplying interpolator; a fine adjusting interpolator, to which the two outputs from the switch are applied, for outputting a signal obtained by internally dividing the phase difference between the two outputs; and a control circuit for controlling the switching of the switch and varying the internal-division ratio of the fine adjusting interpolator.

An analog BIST (Built-in Self-Test) module for a load board in a test system for testing Integrated Chips (IC) and other devices-under-test (DUTs). Components of the test module perform test setup, transmission of analog test signals to a DUT, capture of analog and digital test data from the DUT, and on-board analysis of the test data using DSPs without sending the test data to a tester. Modules may be add-on boards to load boards an contain one or more processors and multiple components to test DUTs in parallel, significantly decreasing test and analysis times of a test system such as a Very Low Cost Tester (VLCT).

A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a first internal clock and a second internal clock; a second delay line for generating a first clock and a second clock; a delay line control unit for controlling the second delay line; a phase control unit for generating a first DLL clock and a second DLL clock by mixing the first clock and the second clock; and a phase comparing unit for comparing the first DLL clock and the second DLL clock with the rising clock to generate a lock signal for controlling an operation timing of the first delay line and the second delay line.

A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL. The second DCO of the output PLL has a control input to introduce a phase offset therein relative to the first DCO of the output PLL. A control unit for sets the phase of the second DCO of the acquisition circuit and the second DCO of the output PLL to a common value during changeover from one input to another to avoid an instantaneous phase error upon switching reference signals.