9940 results about "Tester device" patented technology

A data storage device (DSD) tester for testing a DSD is disclosed. The DSD tester comprises a plurality of bays, a screen, and control circuitry operable to detect when a first DSD has been inserted into a first bay. Independent of operator input, a graphical user interface (GUI) displayed on the screen is automatically updated to reflect the first DSD has been inserted into the first bay. Independent of operator input, a DSD test is automatically executed on the first DSD. When the first DSD is removed from the first bay, independent of operator input, the GUI is automatically updated to reflect the first DSD has been removed from the first bay.

A data storage device (DSD) tester for testing a DSD is disclosed. The DSD tester comprises control circuitry operable to receive a DSD log from the DSD, wherein the DSD log comprises at least one entry identifying at least one error condition. A sequence of commands associated with the error condition is executed in order to determine whether the DSD is defective.

A LAN tester has display and remote units each having a connector jack attached to an adapter board for connection to the plug of a patch cord. Both the display and remote units have circuits which are capable of measuring the phase between a drive signal voltage and the corresponding coupled or reflected signal due to the drive signal. Scattering parameters for the mated connector pairs and the patch cord itself are measured during a field calibration. A computer in one or both of the tester units stores the measured scattering parameters and uses the scattering parameters to move the reference plane to any desired location along the patch cord. Channel link or permanent link tests can be conducted using the same equipment.

A probe system for providing signal paths between an integrated circuit (IC) tester and input / output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I / O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. A flex strip may alternatively be disposed behind a substrate with probes.

A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads. The tester channel measures the voltage of its input signal so that the logic state of the signals produced at each of the N IC output pads can be determined from the measured voltage.

A method and apparatus for simulating a battery tester with a fixed resistance load, such as a widely used Japanese load tester that rates the strength of Japanese batteries that are categorized under the Japanese Industrial Standard (JIS), are provided. This invention simulates such a device without invoking large current loads, yields familiar results, utilizes an existing database and provides more conclusive testing. The method includes measuring an open circuit voltage (OCV), temperature and a dynamic parameter of the battery. A load voltage of the battery is estimated as a function of the measured battery dynamic parameter, the OCV, the load resistance value of the load tester and the battery temperature. A bounceback voltage (BBV) of the battery is then predicted. The BBV, the load voltage and the battery temperature are utilized to rate the strength of the battery.