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2425results about How to "Quick test" patented technology

Method for testing flash memory power loss recovery

ActiveUS20050108491A1Quickly testSave time and resourceRead-only memoriesMemory systemsStorage cellRecovery cycle
Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt / stop execution or simulate power loss at a specific point. This ability allows for a deterministic and repeatable testing process of all write or erase cycles of a non-volatile command where the state of floating gate memory cells are changed in the non-volatile memory device. Additionally, this ability to utilize write or erase cycle tracking to interrupt or stop a non-volatile memory programming operation or erasing operation at any selected point enables simulation of power loss at each point in a selected operation that a non-volatile floating gate memory cell is programmed or erased, allowing for improved, deterministic testing of the power loss recovery cycle and faster code / design change verification.
Owner:MICRON TECH INC

Fine simulation test device and fine simulation test method for slope water erosion

The invention discloses a fine simulation test device and a fine simulation test method for slope water erosion. The fine simulation test device comprises an underframe provided with trundles and a test soil groove connected with the underframe, the test soil groove is arranged above the underframe, one end of the test soil groove is hinged to one end of the underframe, and a water tank matched with the test soil groove is arranged at the other end of the test soil groove. A hydraulic rod is arranged between the test soil groove and the underframe, an equalization pond is arranged between thetest soil groove and the water tank, the equalization pond is communicated with the water tank through a water conveying pipe, the water conveying pipe and a water pump are arranged on one side of the water tank, a water discharging pipe is communicated with the lower portion of the water tank, a three-dimensional laser scanner is arranged in front of the test soil groove, a railfall device is arranged right above the test soil groove, and a flow collecting opening connected with the test soil groove is arranged at the end of the test soil groove hinged to the underframe. The fine simulation test device and the fine simulation test method for the slope water erosion have the advantages of being capable of controlling slope soil bulk density, vegetation types and cover degree manually, simulating soil water erosion conditions under different site conditions, and studying influences and response theories of all factors on soil water erosion under different underlying surface conditions.
Owner:YELLOW RIVER INST OF HYDRAULIC RES YELLOW RIVER CONSERVANCY COMMISSION

Method and system for automatically updating a software QA Test repository

In accordance with embodiments, there are provided mechanisms and methods for automatically updating a software QA test repository in a database system. These mechanisms and methods for automatically updating a QA test repository can enable embodiments to quickly and accurately update a test repository without requiring a user to repeatedly enter test case documentation data. These mechanisms and methods for automatically updating a QA test repository can also enable embodiments to extract plain language descriptions of test cases in the test repository. The ability of embodiments to automatically update the test repository and provide descriptions for the test cases stored in the test repository allows developers to efficiently update and share the contents of the test repository.
Owner:SALESFORCE COM INC

Universal method and platform for verifying compatibility between intellectual property (IP) core and advanced microcontroller bus architecture (AMBA) bus interface

The invention provides a universal platform of verifying compatibility between an intellectual property (IP) core and an advanced microcontroller bus architecture (AMBA) bus interface, which comprises a functional simulation tool, an AMBA bus infrastructure, a third-party verification IP core, a controller, a driver, a stimulus, a checker, an advanced peripheral bus (APB) bridge, an advanced high-performance bus (AHB) master interface, an AHB slave interface and an APB slave interface, wherein all the modules are connected to form an integrated coordinating verification environment by adopting a verification component and hierarchical packaging and interconnections ways provided by a SystemVerilog language and advanced verification methodology (AVM). The platform can verify the compatibility of different types of IP core interfaces, and the development time and cost of the verification platform and a verification method are reduced. The invention also provides the universal method for verifying the compatibility between the IP core and the AMBA bus interface. In the method, excitation is produced more normatively, scientifically and accurately, unnecessary iteration is reduced and the verification time is shortened.
Owner:SHANGHAI SILICON INTPROP EXCHANGE
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