37 results about "Deterministic testing" patented technology

Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entries based on a detected number of receive clock edges within one local clock cycle. Valid data is identified based on the number of clock edges exceeding a selected threshold. A selected pointer offset is obtained from a lookahead table, specifying multiple pointer offsets for accommodating latency encountered at respective prescribed available frequencies, based on matching the determined frequency to one of the prescribed available frequencies. The selected pointer offset is added to a read pointer to offset the latency encountered from edge detection.

Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt / stop execution or simulate power loss at a specific point. This ability allows for a deterministic and repeatable testing process of all write or erase cycles of a non-volatile command where the state of floating gate memory cells are changed in the non-volatile memory device. Additionally, this ability to utilize write or erase cycle tracking to interrupt or stop a non-volatile memory programming operation or erasing operation at any selected point enables simulation of power loss at each point in a selected operation that a non-volatile floating gate memory cell is programmed or erased, allowing for improved, deterministic testing of the power loss recovery cycle and faster code / design change verification.

A method and system for testing packet error rate in electronic devices by transmitting a series of data packets from a testing device to a device under test (DUT) and setting a predefined number of received error-free data packets; evaluating whether a number of data packets from the series of data packets received error-free by the DUT equals the predefined number of received error-free data packets and transmitting additional data packets from the testing device to the DUT, at a power level known to produce zero received-packet errors in a correctly operating DUT, if the number of data packets from the series of data packets received error-free by the DUT does not equal the predefined number of received error-free data packets. Additional possible embodiments include evaluating whether a total number of data packets from the series of data packets and the additional error-free-power-level data packets received error-free by the DUT equals the predefined number of received error-free data packets and transmitting a confirmation data packet to the testing device in response to reception by the DUT of the predefined number of received error-free data packets.

Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.

A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.

Software in an electronic device can be tested using a combination of random testing and deterministic testing. In various embodiments, deterministic tests can run for a prescribed duration and / or a prescribed number of iterations before and / or after random testing. Test results can be weighted using a metric representing an amount of code that was stressed during testing. This metric can be determined by tracking software code that is loaded into memory during testing.

Built-in test equipment (BITE) incorporated in a GPS receiver for providing a loop forward test. The loop forward test capability may be combined with a loop backward capability to provide a comprehensive built-in test (BIT) capability for the signal path in a GPS receiver. A code generator generates deterministic test code signals such as C / A code, P code and pseudo M code that are used to modulate one or more radio frequency (RF) carriers to produce RF test signals. The RF test signals are injected into the GPS receiver's RF input. The RF test signal signals are then down-converted and demodulated through an operational signal path of the GPS receiver. The processed test signals may then be compared to the initial test data. A loop backward BITE may also be used to sample the positioning data output by the receiver.

The object being to develop an integrated circuit arrangement (100) with at least one application circuit (40) to be tested, and with at least one self-test circuit (10, 20, 32, 34, 36, 50) provided for testing the application circuit (40) and generating at least one pseudo-random test sample, wherein said pseudo-random test sample can be converted into at least one test vector that is programmable and / or deterministic and that can be supplied to the application circuit (40) for testing purposes via at least one logic gate (32, 34, 36) and by means of at least one signal that can be applied to said logic gate (32, 34, 36), and wherein the output signal arising in dependence on the deterministic test vector can be evaluated by the application circuit (40) by means of at least one signature register (50), as well as a method of testing the application circuit (40) present in the integrated circuit arrangement (100) by means of the self-test circuit (10, 20, 32, 34, 36, 50) further such that the B[uild-]I[n]S[elf-]T[est] hardware connected to the additional deterministic logic can be reduced, it is suggested that the signal to be supplied to the logic gate (32, 34, 36) can be made available by a B[it]F[lipping]F[unction] logic circuit (10) based on at least one

A novel decompressor / PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor / PRPG has two phases of operation. In a pseudo-random phase, the decompressor / PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor / PRPG. The patterns are decompressed as they are clocked through the decompressor / PRPG into the scan chains. The decompressor / PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

A method and system for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test seeds from a plurality of original test seeds, the generated test seeds and original test seeds defining a total test seed plurality and a subset deterministic test pattern plurality. A response suppression circuit suppresses test responses from the CUT if not generated responsive to a deterministic test seed of the deterministic test pattern plurality.

The invention relates to a method for compressing the test data of integrated circuit, belonging to integrated circuit technical field, in particular to a deterministic self-test test data compressor.The invention comprises a phase shifter, a response compressor, a linear feedback shift register with a first and a second xor network while the shift register is connected with the phase shift, a scanning tree and a weigh random signal generating logic unit while the scan forest is connected with the phase shift, the gating signal end of the scan forest is connected with the weight random signalgenerating logic unit, and the output of the scan forest is connected with the response compressor. The invention further provides a deterministic self-test test data compression method. The invention uses the weight random signal generating logic unit to control the frequency of special signal of the input signal of the scan forest, to improve the fault coverage rate into the false random self-test process, to reduce the test data memory space generated by deterministic test vector.

The present invention discloses a system and method for deterministically testing the packet error rate in electronic equipment, including: transmitting a series of data packets from the test equipment to the device under test (DUT) and setting the error-free data packets received a predetermined number; assessing whether the number of data packets received by the DUT without error in a series of data packets is equal to the predetermined number of error-free data packets received; and if not equal to the predetermined number of error-free data packets received, it will have Additional packets are transmitted from the test equipment to the DUT at a power level that produces zero received packet errors in a correctly functioning DUT. Other possible embodiments include evaluating whether the total number of data packets received without error by the DUT in a series of data packets and additional error-free power level data packets is equal to a predetermined number of received error-free data packets; and in response to the DUT receiving Upon said predetermined number of error-free data packets received, an acknowledgment packet is sent to the test device.

The invention provides a low-power scanning self-test circuit which comprises a phase shifter, a linear feedback shift register, and a multi-input characteristic analysis register. The low-power scanning self-test circuit is characterized in that the low-power scanning self-test circuit further comprises a scanning forest structure; the scanning forest structure comprises multiple scanning trees connected with the phase shifter; each scanning tree comprises multiple scanning chains which are all connected to the input end of the same clock signal so that all the scanning chains of the same scanning tree are driven by the same clock signal; the input end of each test enable signal is connected with all the scanning chains so different weights are assigned to all the scanning chains; in the multiple scanning chains of each scanning tree, each pair of triggers of each scanning chain have no common access nodes, and the triggers close to each other between two scanning chains are connected; and the linear feedback shift register includes a register bit used for saving all deterministic test vectors.