41 results about "Test vector generator" patented technology

Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a vector selecting section that selects test vectors that cause a prescribed characteristic of the device under test, which is to be measured when test signals that are each based on one of the test vectors are supplied to the device under test, to fulfill a preset condition; and a judging section that judges pass / fail of the device under test based on measured values of the prescribed characteristic of the device under test supplied with the test signal based on the test vectors selected by the vector selecting section.

A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.

A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.

The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.

The invention discloses a system and a method for verifying register transfer level (RTL) hardware of a video algorithm. The system comprises a test video sequence library, a test vector generator, a golden C language model, an RTL hardware model to be verified and a file comparator, wherein the test video sequence library is used for storing a test sequence required by verifying the design of the RTL hardware of the video algorithm; the test vector generator is used for selecting the test sequence from the test video sequence library according to the functional coverage of the algorithm, generating a test vector and outputting the test vector to the golden C language model and the RTL hardware model to be verified; the golden C language model and the RTL hardware model to be verified are used for respectively generating output after receiving the test vector and outputting the respective output to the file comparator; and the file comparator is used for comparing whether the output of the golden C language model is consistent with the output of the RTL hardware model to be verified or not, indicating that the RTL hardware passes verification if the outputs are consistent, and indicating that the RTL hardware does not pass verification if the outputs are inconsistent. By the system and the method, the efficiency and correctness of verifying the design of the RTL hardware of the video algorithm are improved.