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35 results about "Random test generator" patented technology

Random test generators (often abbreviated RTG or ISG for Instruction Stream Generator) are a type of computer software that is used in functional verification of microprocessors. Their primary use lies in providing input stimulus to a device under test.

Thermal noise random pulse generator and random number generator

A random number generator has a simple configuration using know inexpensive electronic parts and can generate the true physical random numbers at a required generation speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises Hen no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals. A thermal noise random number generator comprises, in addition to the above components, an n-bit counter (n being an integer) for measuring the time interval between a random pulse signal output from the waveform shaping circuit (6) and the immediately succeeding random pulse signal and is adapted to output the count of the n-bit counter as natural random number.
Owner:L E TECH

Pseudo-random number generator and test system using it

A pseudo-random number generating unit consists of input and output ports for inputting random number sampling range , seed selector , pseudo - random sequence generating unit for generating any length of pseudo - random sequence , positioning device for determining effective bit of random sequence and range adjusting unit for adjust random sequence value . The test device realized by above-said unit can quickly generate large amount of message with different length required by test to let system simulate real data flow accurately for raising test effect.
Owner:HONOR DEVICE CO LTD

Tamper detector with hardware-based random number generator

A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.
Owner:NXP USA INC

Implementing random content of program loops in random test generation for processor verification

A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.
Owner:IBM CORP

Efficient testing of direct memory address translation

ActiveUS10169186B1Efficient stress testing address translationMemory architecture accessing/allocationHardware monitoringMemory addressMain processing unit
A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.
Owner:IBM CORP

Efficient testing of direct memory address translation

ActiveUS10169185B1Efficient stress testing address translationMemory architecture accessing/allocationHardware monitoringMemory addressMain processing unit
A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.
Owner:IBM CORP

Random number generation method and random number generator

InactiveCN106383691ASolve the problem of XOR attackRandom number generatorsDigital signal processingS-box
The invention relates to a random number generation method and a random number generator. The method comprises the steps that a plurality of physical random sources perform digital processing on a generated physical signal and sends a digital signal obtained by processing to an S box; the S box performs nonlinear replacement processing on the digital signal and outputs a replacement processing result to an XOR module; the XOR module performs XOR processing on the replacement processing result and outputs an XOR processing result to a post-processing module; and the post-processing module eliminates a deviation and a dependency relationship in the XOR processing result and outputs a random number. According to the random number generation method and the random number generator provided by embodiments of the invention, the problem of XOR attack of the physical random sources is effectively solved; and even if an attacker attacks an input of a physical random source in the XOR position, an input of post-processing still contains information of the random source because the S box has the characteristic of a confusion property.
Owner:BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY +4

Dynamic generation of test segments

A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a target computerized system, the test template comprises a template segment, the template segment comprising one or more instruction and one or more directives or control constructs related to the instructions; a test generator for generating a test associated with the template segment, said test generator comprises: a state simulator for determining a state of the target computerized system associated with an execution of the test; a template instruction or segment selector for selecting a template instruction or segment from the test template based on the state of the target system determined by said state simulator; and an instruction template segment generator configured to generate a multiplicity of instructions based on the state of the target computerized system and the template segment selected by said template instruction selector, wherein the test generator further comprises an instruction verifier configured to verify that a previously generated instruction is in line with the current state of the target computerized system and with the template instruction or segment selected by said template instruction or segment selector.
Owner:GLOBALFOUNDRIES INC

Pseudo-random squence generator and associated method

A method, and associated apparatus, for generating a pseudo-random number sequence. Determinations are made of compatible configurations of windmill generators for a selected windmill polynomial. Implementation of a windmill generator is made through use of word-oriented memory elements. Words stored in the memory elements are selectively outputted to form portions of a pseudo-random number sequence.
Owner:TELEFON AB LM ERICSSON (PUBL)
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