174 results about "Test generator" patented technology

Computer system and method automatically generates a test source code for checking validity of an application written in an object oriented language. The application includes objects accessible through an interface implementing programming rules and object behavior rules. For each object, the invention extracts object methods and attributes of the object interface which are impacted by the object behavior rules and extracts the object identification. The invention fills the variable fields of a source code template with the extracted information. The template non variable source code is in conformance with the programming rules and implements a scenario for checking a set of object behavior rules; thus the filled template forms a generated test source code. For distributed applications, the specifications may be EJB or CORBA and the Test Generator uses templates for checking the life-cycle (creation, persistency, removal) of deployed objects.

Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators / receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator / receiver is associated with each of the plurality of ports. Under software control, test packets can be sent from at least any one of the plurality of ports to at least any other one of the plurality of ports. In this way, an in-circuit testing procedure may be implemented without having to disconnect line cards from the switch and connect the switch to expensive external test equipment.

Middleware is validated using a two layered modeling strategy for the generation of test suites. A high level model of the syntax of the programming language used to program the middleware generates a series of high level abstract programs. These high level abstract programs then undergo two separate translations. First they are translated directly into actual test programs, which are expressed in the programming language of the middleware. Second, they are translated into second models of the high level abstract programs. Running the model based test generator again on the second models produces a set of suites of test cases, each test case consisting of data inputs and predicted results for one of the actual test programs. The actual test programs are run repetitively using the middleware execution engine. The results are compared with the predicted results, using a generic validation engine.

A system, method and data structure for testing a web location including a web site or web service. A test generator or user generates an XML test case and a driver interprets the XML test case into an http request to be sent to the web location as a test.

Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.