52 results about "Standard Delay Format" patented technology

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

The invention discloses a client complaint early-warning monitoring analyzing method based on text mining technology. The method comprises the steps of a text data standardizing step for converting recorded text data into data with a standard data format in a unified rule; and a standard data analysis early-warning step, analyzing the standard data format through establishing a complaint analysis grade clustering model, determining a risk grade according to the clustering result, and transmitting early-warning according to the risk grade. The complaint early-warning monitoring analyzing method satisfies a precondition of ensuring client satisfaction degree and furthermore has advantages of greatly reducing workload in manual sampling observation, effectively improving passive after-event tracking responsibility-determining management mode and facilitating before-event active server in a targeted manner, thereby realizing a professional management requirement for in-time response for client demands.

A system and method is described for receiving a plurality of non-standardized data sets and generating respective plurality of standardized profiles that can be used for efficiently comparing and matching one profile against the other plurality of profiles. One application of this invention is to convert job seekers' resumes and job postings into respective profiles and then permitting either a job seeker to search for job postings that most closely match the job seeker's resume or, conversely, permitting an employer to search for job seekers whose resumes most closely match the employer's job posting.

The invention relates to an interface method in the field of electric power system dispatching, in particular to a standard data exchange interface method of a parallel cooperative system. Data transmission between a database in the parallel cooperative system and an external data source is carried out through a data exchange interface; transmitted data adopt standard data formats; standard data adopt power grid data in E-language formats. The standard data exchange interface method comprises the following steps of (1) initializing an Oracle database; (2) reading a file in the E-language format to a memory; (3) copying in a list-to-list way; (4) writing the data to the Oracle database. According to the standard data exchange interface method disclosed by the invention, the problem of importing the data in different formats to the database is solved, and the defects such as manual data conversion and repeated operation which are caused by discrete of a daily traditional mainstream algorithm can be eliminated.

The invention discloses an implementation method for an integrated exchange platform. The implementation method includes the following steps that the integrated exchange platform independent from service applications is established; standard data formats inside the platform are defined through the integrated exchange platform; different information formats and grammars are reconverted into data formats and semantics capable of being understood by a target application system through data format conversion and data semantic conversion; all service requests are sent to the integrated exchange platform in a centralized mode, then the requests are recognized, a provider and a request forwarding route of services are determined through a route scheduling module arranged in the integrated exchange platform, and the service requests are forwarded to the actual service provider. Compared with the prior art, by means of the implementation method for the integrated exchange platform, multiple independent technologies are integrated to achieve the function of maintaining stable and efficient operation of a whole system, good compatibility is achieved, and the method is suitable for automatically acquiring data of multiple data sources, high in practicality and easy to popularize.

The invention relates to a statistics data integration method and system. The integration method comprises the following steps of obtaining and arranging metadata, and describing the metadata according to a preset description standard to obtain description information; obtaining a data file, and associating the data file with the description information to generate a file in a standard format; and analyzing the file in the standard format to obtain a standard information model file, and performing storage. The method and the system have the beneficial effects that statistics business personnel can be facilitated to perform standard description on data, and the formed description information can be directly used by computer systems, so that the statistics data integration quality and efficiency are greatly improved.

The invention provides a method for generating a gate-level netlist and a standard delay file and checking and correcting false routes. The method for generating the gate-level netlist and standard delay file comprises the steps: acquiring all false routes; for each false route, executing the following operations: obtaining all fan-in and fan-out of each object on the false route, analyzing whether delay points exist in the fan-in and fan-out of each object, if so, defining no delay point to the false route any more, and if not, defining delay points according to the type of a time sequence arc between the fan-in and fan-out; and defining delay values to the delay points of the false route and writing a standard delay file and a modified gate-level netlist. Delay is added to the delay points so as to generate the standard delay file and the modified gate-level netlist and further check the set correctness of the false routes, so that the serious problems in the false routes can be found out before layout wiring is carried out, the layout wiring production period can be shortened, and the repeated layout wiring can be avoided.

The invention provides a time sequence correction method. The method comprises the following steps: performing static timing analysis according to a netlist file, a first timing constraint file and a parasitic parameter file, so as to generate a first standard delay file and a log file; judging whether design rule violations occur through a first script and according to the log file; when judging that the design rule violations occur, generating a violation component list, and a second timing constraint file of a maximum set value allowed by a corresponding design rule through the first script; and judging whether to correct a timing path according to the second timing constraint file.

The invention provides a method and a device for generating a standard delay format file. The method comprises the following steps: according to a standard cell library and an input file used by a chip, carrying out time sequence analysis on the chip, and determining a standard cell of a time sequence violation; Replacing the standard unit of the time sequence violation with a virtual unit of thestandard unit of the time sequence violation meeting the Setup / Hold time sequence requirement to obtain a tcl format file for repairing the time sequence; According to the tcl format file, generatinga standard delay format file meeting a Setup / Hold time sequence requirement; And modifying the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard time delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard time delay format file. According to the method, the SDF file meeting the Setup / Hold time sequence requirement at the early stage of back-end time sequence convergence can be generated under the condition that a netlist is not changed.

A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the digital output circuit connected to the analog output circuit to obtain an ideal output, obtaining a first delay time according to the standard delay times of the digital output circuit, performing a calibrative analog-to-digital mixed mode simulation using the first delay time to obtain an analog-to-digital mixed output, comparing the ideal output and the analog-to-digital mixed output to calibrate the first delay time, and calibrating the standard delay times of the digital output circuit according to the calibrated first delay time.

The invention provides a musical instrument performance analysis method. The method comprises steps: audio acquisition is carried out; Hanning window applying is carried out on an acquired sample; an FFTW transform library is used for acquiring a frequency domain spectrogram; frequencies with a small height are neglected during the frequency domain spectrogram processing process for noise reduction, positions with wave crest features are processed, and the frequency at the point is obtained and recorded; all wave crest features are processed, and a corresponding frequency list is obtained; and according to a standard frequency check list of a key, a performance staff is obtained. The evaluation method comprises steps: a standard audio format is acquired; a standard staff is obtained according to the standard audio format; and the performance staff and the standard staff are compared to evaluate the performance of the user. Through adopting the above method, real-time guidance and feedback can be carried out, the user can be more effectively guided to learn by himself or herself, and self learning in an environment without guidance by the teacher can be completed.

The invention discloses a timing constraint checking method, and belongs to the technical field of layout design. The method comprises the following steps of: A1: according to a hardware code related to the layout design, carrying out processing to obtain a corresponding netlist; A2: according to the netlist, carrying out simulation to generate corresponding standard delay data; A3: according to the standard delay data, carrying out a post simulation operation on the layout design so as to match with a timing constraint file used for representing the design constraint of the layout design, and outputting a matching result; A4: according to the matching result, regulating the timing constraint file until the matching result expresses that post simulation is qualified, and then, turning to A5; and A5: carrying out corresponding timing checking on the layout design, and exiting. The above technical scheme has the beneficial effects that a timing constraint checking process is brought forward to be simultaneously carried out with a P&R (Place& Route) process, and the problems that an error influence is great and extra human cost needs to be paid since a timing constraint problem is found too late are solved.

The embodiment of the invention discloses an automatic configuration method used for avoiding the situation that error data are configured into a cloud compiling system when manually configured, ensuring stable operation of the cloud compiling system and automatically configuring attribute configuration information into the cloud compiling system, and use is convenient. The automatic configuration method comprises the steps that 1, a standard file format of procedure codes is obtained and is generated by macro definition information of the procedure codes; 2, the macro definition information of the standard file format is extracted; 3, the macro definition information is converted into function unit configuration information according to a preset function unit mapping table; 4, the attribute configuration information is obtained according to a preset attribute resolution mode and the function unit configuration information, and the attribute resolution mode comprises the corresponding relation between the function unit configuration information and the attribute configuration information; 5, the function unit configuration information and the attribute configuration information are stored. The embodiment of the invention further provides the cloud compiling system.

The invention discloses a data processing method and device, relates to the technical field of communication network, and aims to solve the problem of refining different services of a user and an application service. The method comprises the following steps: receiving all EPS (Evolved Packet System) bearers through an eNB (evolved Node B), acquiring SDF (Standard Delay Format) information and EPS bearer information carried by a data packet on each EPS bearer, mapping the SDF information and the EPS bearer information carried by the data packet on each EPS bearer into corresponding extension QoS (Quality of Service) parameter of the data packet on the EPS bearer; distributing wireless resources to the data packet on each EPS bearer according to the corresponding extension QoS parameter of the data packet on the EPS bearer. The scheme provided by the embodiment is suitable for processing data.

A digital circuit design method includes: before performing physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraint file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.

The invention discloses a data integration system for grid state detection, and an implementation method of the data integration system. The method comprises the following steps of: classifying grid state detection systems according to detection objects; establishing a special database for storing original detection data of various state detection systems; establishing a standard database for storing unified grid equipment ledger information; establishing standard data formats of various state detection systems, converting the original detection data into the standard data formats, and associating the standard data formats with the corresponding grid equipment ledger information; and publishing the data. By the invention, the problems of inconvenience in use, difficulty in integration and the like caused by difference in transmission modes of different manufacturers of the grid state detection systems and data heterogeneity are solved. Meanwhile, a unified and integrated data storage and publishing mode is provided, so that a user can acquire all data through a platform. By establishing the unified grid equipment ledger information in the standard database, the equipment ledger maintenance workload of a maintainer is reduced, working efficiency is improved, and labor cost is reduced.

The invention provides a symmetric key generation and distribution time sequence aiming method based on wireless channel characteristics. The method includes the steps of NTP clock synchronization, characteristic extraction, time format conversion and time sequence aiming. NTP clock synchronization is used for synchronizing local clocks of two key generation parties. Characteristic extraction is used for acquiring wireless channel characteristic values of the intensity, the phase and the Doppler frequency shift of received signals from a wireless communication system. Time format conversion is used for converting a standard time format into a cumulative time format. Time sequence aiming is used for enabling the channel characteristics of the two key generation parties to correspond one to one according to a time axis. The method solves the problems that the numbers of data of wireless channel characteristic sequences on two communication parties are inconsistent and the wireless channel characteristic sequences do not correspond one to one on the time axis, the matching ratio of symmetric keys in the generation process is increased, and development of the next-generation symmetric key technology is powerfully supported.

Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.

The invention provides a digital circuit design method and a related system. The digital circuit design method comprises the following steps: before performing substantive design, performing logic synthesis according to the transfer-level design of a register and multiple constraints so as to at least generate a netlist file, a standard delay format file, and a first constraint file; extracting information of at least one specific node in a circuit from the first constraint file so as to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein the delay amount of the specific node in the updated standard delay format file is less than that of the specific node in the standard delay format file; and performing advance circuit post-layout simulation by using the netlist file and the updated standard delay format file.

The invention provides an IPTV hardware encryption transmission broadcast control system for the features of large video data volume transmitted on an IPTV network and high requirements for real-time performance and continuity. The system is formed by a scrambling machine (002), a conditional access system (CAS) server (003), a subscriber management system (SMS) server (004), a program storage video server (005), a general clear stream IPTV set top box (006) and a USB video hardware decryption disc (007). The video stream is subjected to real-time encryption and decryption processing through special hardware equipment in the whole transmission process; the encrypted real-time or non-real-time large-data-volume videos are transmitted on the internet; and the system is specially provided with the scrambling machine (002) for carrying out encryption and decryption on the video stream through hardware and the USB video hardware decryption disc (007), utilizes the standard DVB transport stream (TS) as a system transmission basic data format, and supports various standard video formats, including MPEG1, MPEG2, H264 and H265 and the like, as well as data transmission protocols of UDP, HTTP and HLS and the like.

One or more embodiments of the invention provide a compiling method for logic system design, electronic equipment and a storage medium. The logic system design comprises a plurality of modules distributed at a plurality of levels. The method comprises the steps of obtaining a first standard delay format file corresponding to the logic system design; generating a tree structure corresponding to the logic system design according to the description of a plurality of signals in the standard delay format file, the tree structure comprising a plurality of branches composed of a plurality of nodes; generating a plurality of codes respectively corresponding to the plurality of branches, wherein the codes are used for replacing descriptions of a plurality of signals in the first standard delay format file to generate a second standard delay format file; and compiling the logic system design based on the second standard delay format file and the tree structure.

An EDA tool for verifying timing constraints of an integrated circuit (IC) design includes a processor and a memory that stores register transfer level (RTL) code of the IC design and a timing constraint file. The processor generates a netlist based on the RTL code, and identifies asynchronous clock paths, false paths and multi-cycle paths in the netlist using the timing constraint file. The processor then inserts buffer cells for logic cells in the netlist. The processor also inserts buffer cells in the asynchronous clock paths, false paths, and multi-cycle paths. The processor delay annotates logic cells and clock delay cells with a zero delay value and the buffer cells with known delay values. The processor generates a modeled standard delay format (SDF) file and performs a gate level simulation (GLS) using the modeled SDF file.

The invention relates to the field of on-line video transmission, disclosing an on-line video transmission method and system. By utilizing the on-line video transmission method and system provided by the invention, the obtained video data of each on-line video service website is formatted into the video data of a standard data format conforming to the browsing and access of an intelligent online terminal, and the intelligent online terminal is used for browsing and using the video data; when new online service is adjusted or added, a terminal user does not need to passively adopt the following behaviour of updating software at all, thereby solving the problem that the firmware of the terminal equipment is forcedly and frequently updated for adapting to new Internet online service, realizing the updating and deploying of the firmware, and bringing convenience for users.

The invention provides a security analysis method and system for encryption equipment with a mask combination circuit. A cross-correlation analysis result between an overturning counting model and anactual measurement power consumption curve of encryption equipment is calculated; an optimized flip count model is determined, and finally, the safety performance of the encryption equipment is testedby utilizing the optimized flip counting model, so that the influence caused by the difference between the reverse annotation information obtained by simulation and the real delay in the actual circuit is eliminated, the simulation precision is improved, and the effectiveness of the flip counting model applied to the safety analysis of the encryption equipment is further improved. Meanwhile, theoptimization scheme only needs to combine with an actual measurement power consumption curve to correct the delay information in the standard delay format file so as to achieve the purpose of model optimization, and the method is simple and efficient.

A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are impossible to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.

Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.

The invention discloses a method for detecting a 3G-SDI image in a non-standard format. The method achieves the detection of the full resolution and frame frequency of the 3G-SDI image in the non-standard format, thereby achieving the effective evaluation of the correctness of a data source of a transmitting end and the problems that whether frame loss exists in a data transmission process or not.The method comprises the following three detection modes: mode 1, full-resolution detection of an image; mode 2, image frame frequency detection; and mode 3, detection of image display effect.