1967 results about "Frequency detection" patented technology

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

A video signal including illumination flicker component is integrated at each of unit areas (horizontal lines) in a frame (field) of the video signal. The integrated level at each of the unit areas at the frame and the integrated level at the corresponding unit area of an adjacent frame are averaged. Dividing is effected between results of the averaging and integrating every unit area. It is judged whether flicker exists in the video signal by frequency-analyzing results of the dividing result at the unit areas. The unit area may be plural adjacent lines where flickering are negligible. The averaging circuit may be circulation type of or FIR filter. Threshold level for judging the flicker is changed according to a shutter speed control signal. Flicker compensation may be executed by controlling shutter speed or the AGC according to flicker judging result. A still condition at a block in a frame may be detected from the integration result at plural frames. When the block is judged to be still, the flicker is judged. An ac line frequency detection is also disclosed to detect the frequency of the ac line from a video signal generated under illumination including flicker. An imaging circuit may be provided to generate the video signal therein.

The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).

A method and system for use in creating a profile of, managing and understanding power consumption in a premise of a user, wherein said premise comprises two or more power consuming devices comprises measuring, via at least one sensor, aggregate energy consumption at the premise, receiving at a mobile computing device comprising a data processor, said aggregated signal from the sensor, collecting and recording the aggregate signal over a plurality of time resolutions and frequencies, therein to create a predicted aggregate signal for each time x and frequency y, detecting changes in the predicted aggregate signal at time x an frequency y (detected consumption pattern changes) and conveying to at least one of the user, a utility company, and other third party a notification of detected consumption pattern changes.

Demodulation apparatus includes a transversal filter characterized by coefficients adjusted by a coefficient determiner responsive to a constant modulus error signal and variable mode error signal related to the output of a spectral mean frequency detector having its input coupled to the output of the transversal filter.

An adaptive frequency controller, a phase-locked loop including the same and an adaptive frequency controlling method are provided. In an adaptive frequency controller, a frequency detector compares a frequency of a first signal with a frequency of a second signal. A state machine adjusts a code position based on a lo result of the comparison of the frequencies of the first and second signals. An initial code generator receives a locking frequency, determines an estimation code, and sets a code range to be searched. An AFC code generator generates a code value from the determined estimation code based on the code position of the state machine.

A high frequency amplifier circuit includes the voltage source supplying the power source voltage on the output side of the high frequency amplifying active element. The high frequency amplifier is constructed with a voltage detector detecting a difference frequency voltage of the input signal at a frequency lower than the input signal of the high frequency amplifier circuit and control portion for attenuating the difference frequency voltage from the output signal by controlling the power source voltage on the basis of the difference frequency voltage detected by the voltage detector. Therefore, distortion due to modulating the input signal with the difference frequency component of the input signal can be reduced.

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

An object is to provide a power feeding system and a power feeding method which are more convenient for a power feeding user at the power receiving end, without causing increases in complexity and size of devices. An object is to provide a power feeding system and a power feeding method which also allow a power feeding provider (a company) which feeds power (at the power transmitting end) to supply power without waste. A power feeding device which wirelessly supplies power to a power receiver detects the position and the resonant frequency of the power receiver by receiving a position and resonant frequency detection signal using a plurality of sub-carriers having different frequencies from the power receiver, and controls the frequency of a power signal to be transmitted to the power receiver on the basis of the information. An efficient power feeding service can be offered by transmitting a power signal to the power receiver at an optimum frequency for high power transmission efficiency.

A steady state frequency control circuit for a variable frequency regulator including an open loop frequency control circuit, a frequency detector and a comparator circuit. The variable frequency regulator provides a clock signal indicating actual operating frequency and has a frequency control parameter for adjusting steady state operating frequency. The frequency detector receives the clock signal and provides a frequency sense signal which is compared with a steady state frequency reference signal to provide a frequency adjust signal. The frequency control parameter is adjusted by the frequency adjust signal to control steady state frequency. A method of controlling steady state frequency of a variable frequency regulator includes using open loop frequency control, determining the operating frequency and providing a frequency sense signal, comparing the frequency sense signal with frequency reference signal and providing a frequency adjust signal, and adjusting the frequency control parameter based on the frequency adjust signal.

An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used to determine which of two possible modes of operation, a referenceless or reference clock mode of operation, is used based on a detected frequency of an externally-provided frequency reference signal. The frequency is detected without any additional externally provided signal to indicate the mode of operation or the frequency of the reference clock. If the frequency detection circuit detects a frequency below a predetermined threshold, referenceless mode of operation is indicated. Otherwise, reference clock mode of operation is indicated. In referenceless mode of operation such operations as frequency acquisition and lock detect are performed without the use of a reference clock. In reference clock mode the reference clock is used for such operations as frequency acquisition and lock detect.

A programmable control unit for a vacuum cleaning system, such as central vacuum cleaning system. A control unit is programmed after manufacture to execute a particular control program for performing various diagnostic and operational functions including user interface, voltage level detecting, voltage monitoring, current monitoring, user interface, power supply control, temperature monitoring, AC line frequency detection, operation data recording, speed control program selection, expansion bus interface and service tool interface. Power control to the vacuum motor is facilitated by the control unit directly through a triode for alternating current (TRIAC). Manufacturing costs are reduced by producing a single programmable control unit that can be programmed with a control program corresponding to a variety of different vacuum cleaning devices across a manufacturer's product line.

A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit is provided. A request signal is sent to the clock, and in response, the clock lowers the clock frequency supplied to the integrated circuit. A frequency detection circuit monitors the clock signal and causes a voltage regulator to reduce the voltage supplied to the integrated circuit in response to the reduced clock frequency. Similarly, a request signal is sent to the clock, and in response, the clock raises the clock frequency supplied to the integrated circuit. The frequency detection circuit monitors the clock signal and causes a voltage regulator to raise the voltage supplied to the integrated circuit in response to the increased clock frequency. The slew rate of the clock is controlled so that at least a minimum required voltage for each operating frequency is provided while the clock frequency is being changed. In this manner, reliable operation of the processor is assured while the clock speed and operating voltage are being changed.

The use of a circuit to adjust the resonance frequency of a high temperature superconductor self-resonant transmit, receive, or transmit and receive coil results in improved performance. The circuit is useful in a frequency detection system, especially in a nuclear quadrupole resonance detection system.

The invention discloses a micromechanical silicon-based clamped beam-based frequency detector and a detection method. The frequency detector comprises a power divider (P), a 90-degree phase shifter (Y), a low-pass filter (L) and a silicon-based metal-oxide-semiconductor field effect transistor; and the power divider is used for receiving a microwave signal to be detected and dividing the microwave signal to be detected into two branch signals with the same amplitude and phase. The detection method includes the following steps: when a direct-current offset is loaded on a first pull-down electrode (81) and a second pull-down electrode (82) and a clamped beam (7) is pulled down and is in contact with a grid (5), two channels of microwave signals are simultaneously loaded on the grid (5), the silicon-based metal-oxide-semiconductor field effect transistor is in a frequency detection state, the saturation current output between a source (2) and a drain (3) contains the current component of the frequency information of the signal to be detected, and by detecting the magnitude of saturation current, frequency detection is finally fulfilled. The structure of the frequency detector is simple, and measurement is easy.

The invention relates to an island detection method of a photovoltaic grid-connected system. In views of the problems that independently-adopted passive detection mode is effective only when effective when mismatching degrees of source and load are large and a large non-detection zone (NDZ) can be accordingly provided; and when an active detection mode is independently-adopted, the system is disturbed, and therefore the disturbance results in instability of the system, and accordingly over-voltage / under-voltage is provided. An over-frequency / under-frequency detection method is combined with an improved impedance detection method to conduct island detection to the system, and therefore the NDZ is reduced to a minimum, quality of electric energy is improved and total harmonic distortion (THD) is reduced.