Time sequence correction method and electronic device

Abstract

The invention provides a time sequence correction method. The method comprises the following steps: performing static timing analysis according to a netlist file, a first timing constraint file and a parasitic parameter file, so as to generate a first standard delay file and a log file; judging whether design rule violations occur through a first script and according to the log file; when judging that the design rule violations occur, generating a violation component list, and a second timing constraint file of a maximum set value allowed by a corresponding design rule through the first script; and judging whether to correct a timing path according to the second timing constraint file.

Description

technical field [0001] This manual mainly relates to the technique of timing correction, and in particular to the technique of correcting only the timing path where a violation occurs through a designed script. Background technique [0002] In the chip design process, in order to ensure that the actually produced chip can work normally in various environments (that is, the sequence meets the requirements), the chip designer will use the static timing analysis tool (StaticTimingAnalysistool, STAtool) and the process provided by the factory. File (processfile) to simulate the timing information of the design in different environments, and then evaluate whether the design meets the timing requirements. [0003] In order to ensure the timing consistency of design and manufacturing, chip manufacturers will provide chip designers with relevant design rules (such as the maximum signal conversion time), which describe the process boundary conditions (boundary conditions) of electric...

AI Technical Summary

Problems solved by technology

However, not every component that violates the design rules is a timing violation, and some even have no timing checks

Therefore, the above method will lead to the insertion of a large number of redundant components, thus increasing the power consumption of the chip, and even the design of some components with dense distribution will lead to deterioration of timing, prolong the chip design cycle, and increase the cost of chip design

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