Compiling method for logic system design, electronic equipment and storage medium

Abstract

One or more embodiments of the invention provide a compiling method for logic system design, electronic equipment and a storage medium. The logic system design comprises a plurality of modules distributed at a plurality of levels. The method comprises the steps of obtaining a first standard delay format file corresponding to the logic system design; generating a tree structure corresponding to the logic system design according to the description of a plurality of signals in the standard delay format file, the tree structure comprising a plurality of branches composed of a plurality of nodes; generating a plurality of codes respectively corresponding to the plurality of branches, wherein the codes are used for replacing descriptions of a plurality of signals in the first standard delay format file to generate a second standard delay format file; and compiling the logic system design based on the second standard delay format file and the tree structure.

Description

technical field [0001] One or more embodiments of this specification relate to the technical field of computer software, and in particular to a compiling method for logic system design, electronic equipment, and storage media. Background technique [0002] In the field of verification of integrated circuits, simulation generally refers to compiling the logic system design and running it on a computer to simulate and test various functions of the logic system design. For the logic system design using computer to simulate hardware, the simulation software cannot provide the timing characteristic information of the actual hardware running, and it is necessary to use the standard delay format file to provide additional timing characteristic information to realize the simulation of the actual running timing characteristics. [0003] The standard delay format file includes signals corresponding to multiple modules in the logic system design. When using the standard delay format fi...

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Problems solved by technology

[0003] The standard delay format file includes signals corresponding to multiple modules in the logic system design. When using the standard delay format file for simulation in the prior art, the module address is searched in sequence according to the order of the signal description format in the file. This method is for the same module The address will be searched multiple times, which greatly increases the simulation compilation time and reduces the efficiency of work execution

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