2111 results about "Exception handling" patented technology

A control system for an RFID-based system for assembling and verifying outbound surgical equipment corresponding to a particular surgery. A user enters a identification number of a surgery. The control system queries a database of surgery information and outputs a list of required surgical equipment, such as surgical instrument sets. An operator uses the list to pick instrument sets for loading into a shipping tote. Each set is tagged with an RFID inventory tag that stores identification information for that set such as a set name and ID number. The shipping tote is passed through an RFID reader and identification data read from the tags is compared against the identification data for sets required for that surgery. A status indicator is activated to alert a user as to whether the surgery is complete that is, all expected sets are present, or that exception handling is required. The control system updates a database such as an ERP system to reflect that the surgery including the required sets has shipped—and the sets are inventoried out to the intended recipient.

A configuration system and method is disclosed that includes a unified and integrated configuration that is composed of a payment system, an advertising system, and an identity management system such that the unified system has all of the benefits of the individual systems as well as several additional synergistic benefits. Also described are specific configurations including the system's access point architecture, visual wallet simulator user interface, security architecture, coupon handling as well as the system's structure and means for delivering them as targeted advertising, business card handling, membership card handling for the purposes of login management, receipt handling, and the editors and grammars provided for customizing the different types of objects in the system as well as the creation of new custom objects with custom behaviors. The configurations are operable on-line as well as through physical presence transactions.

A processing system includes process modules, load lock modules, an equipment controller, and a machine controller. The equipment controller controls transfer and processing of wafers in the processing system. A transfer destination determining portion determines the transfer destination of each wafer such that each wafer is sequentially transferred to a normally operating process module. When an abnormality occurs in a process module, an evacuation portion temporarily evacuates to a cassette stage the wafer determined is to be transferred to the abnormal process module and that has not yet been transferred to the abnormal process module. When a new transfer destination of the evacuated wafer is determined, if a process that is performed immediately before processing the evacuated wafer in the processing module as the new transfer destination satisfies a predetermined condition, a transfer inhibition portion inhibits the transfer of the evacuated wafer to the new transfer destination.

Mechanisms have been developed for securing computational systems against certain forms of attack. In particular, it has been discovered that, by maintaining and propagating taint status for memory locations in correspondence with information flows of instructions executed by a computing system, it is possible to provide a security response if and when a control transfer (or other restricted use) is attempted based on tainted data. In some embodiments, memory management facilities and related exception handlers can be exploited to facilitate taint status propagation and / or security responses. Taint tracking through registers of a processor (or through other storage for which access is not conveniently mediated using a memory management facility) may be provided using an instrumented execution mode of operation. For example, the instrumented mode may be triggered by an attempt to propagate tainted information to a register. In some embodiments, an instrumented mode of operation may be more generally employed. For example, data received from an untrusted source or via an untrusted path is often transferred into a memory buffer for processing by a particular service, routine, process, thread or other computational unit. Code that implements the computational unit may be selectively executed in an instrumented mode that facilitates taint tracking. In general, instrumented execution modes may be supported using a variety of techniques including a binary translation (or rewriting) mode, just-in-time (JIT) compilation / re-compilation, interpreted mode execution, etc. Using an instrumented execution mode and / or exception handler techniques, modifications to CPU hardware can be avoided if desirable.

A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

A model predictive control apparatus includes an initial solution generation section, an abnormality handling section, and an objective function adjustment section. The abnormality handling section performs initial solution generation when it is determined that performed optimization is abnormal. The initial solution generation section generates an initial optimal value of a future time series control input in accordance with an initial objective function, without reference to a candidate value of the time series control input. The objective function adjustment section adjusts the current objective function so that the current objective function varies stepwise with time toward the normal objective function when it is determined that the current objective function is different from the normal objective function.

A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.