424results about How to "Reduce dynamic power consumption" patented technology

A capacitive touch sensor system and method incorporating an interpolated sensor array is disclosed. The system and method utilize a touch sensor array (TSA) configured to detect proximity/contact/pressure (PCP) via a variable impedance array (VIA) electrically coupling interlinked impedance columns (IIC) coupled to an array column driver (ACD), and interlinked impedance rows (IIR) coupled to an array row sensor (ARS). The ACD is configured to select the IIC based on a column switching register (CSR) and electrically drive the IIC using a column driving source (CDS). The VIA conveys current from the driven IIC to the IIC sensed by the ARS. The ARS selects the IIR within the TSA and electrically senses the IIR state based on a row switching register (RSR). Interpolation of ARS sensed current/voltage allows accurate detection of TSA PCP and/or spatial location.

A resistive touch sensor system and method incorporating an interpolated sensor array is disclosed. The system and method utilize a touch sensor array (TSA) configured to detect proximity/contact/pressure (PCP) via a variable impedance array (VIA) electrically coupling interlinked impedance columns (IIC) coupled to an array column driver (ACD), and interlinked impedance rows (IIR) coupled to an array row sensor (ARS). The ACD is configured to select the IIC based on a column switching register (CSR) and electrically drive the IIC using a column driving source (CDS). The VIA conveys current from the driven IIC to the IIC sensed by the ARS. The ARS selects the IIR within the TSA and electrically senses the IIR state based on a row switching register (RSR). Interpolation of ARS sensed current/voltage allows accurate detection of TSA PCP and/or spatial location.

A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

A touch sensor detector system and method incorporating an interpolated sensor array is disclosed. The system and method utilize a touch sensor array (TSA) configured to detect proximity/contact/pressure (PCP) via a variable impedance array (VIA) electrically coupling interlinked impedance columns (IIC) coupled to an array column driver (ACD), and interlinked impedance rows (IIR) coupled to an array row sensor (ARS). The ACD is configured to select the IIC based on a column switching register (CSR) and electrically drive the IIC using a column driving source (CDS). The VIA conveys current from the driven IIC to the IIC sensed by the ARS. The ARS selects the IIR within the TSA and electrically senses the IIR state based on a row switching register (RSR). Interpolation of ARS sensed current/voltage allows accurate detection of TSA PCP and/or spatial location.

An active matrix electrowetting on dielectric (AM-EWOD) device which includes a plurality of array elements configured to manipulate one or more droplets of fluid on an array, each of the array elements including a corresponding array element circuit. Each array element circuit includes a top substrate electrode and a drive electrode between which the one or more droplets may be positioned; circuitry configured to write data to the corresponding array element by selectively applying to the drive electrode either: (i) a time-varying voltage waveform V₁ of amplitude V_B and period t₀; or (ii) a time-varying voltage waveform V₂, the logical inverse of V₁, and applying to the top substrate electrode the time-varying voltage waveform V₂+V_offset, where V_offset represents an offset voltage signal which may have AC and/or DC components and may equal zero.

Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x10¹⁹ (atoms/cm³) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

The invention relates to a gate driving circuit and a display device. The gate driving circuit comprises multiple levels of driving circuit units connected in series. Each level of units comprises an inputting module for providing threshold voltage of a driving module, a driving module for responding to the threshold voltage and for sending a first clock signal to a signal outputting interface, a discharging module for responding to an output signal or a clock signal of an adjacent level and for coupling a control terminal of the driving module to a first voltage source, a clock feedthrough inhibiting module for stablizing the potential of the control terminal of the driving module under the control of the clock signal and the output signal of the adjacent level, and a low level maintaining module for stablizing the output signal at the potential of the first voltage source under the control of the clock signal. The driving circuit unit, gate driving circuit and display device provided by the invention employ single driving tube to realize the fast pull-up and pull-down of the output signal with sequential coordination, reducing the delay time of the rise and fall of the output signal at a low temperature, and employs the clock feedthrough inhibiting module to stablize the gate potential of the driving tube, reducing the corresponding dynamic power consumption.

A low-power-consumption source driver for a liquid crystal display is provided. Morethan one middle voltage level for the level shifter and the output buffer is provided, in addition to the power supply voltage level VDD and the ground level GND, to provide different voltage levels for image data of different polarities. Hence, amplitude of the operational voltage of the level shifters and the analog circuits with different polarities can be reduced. It also can reduce the amplitude of the operational voltage of the level shifter and can reduce significantly the dynamic power consumption of the level shifter and the DAC. Because the voltage amplitude of the circuit is reduced and a low-voltage tolerated device can be used, so that the present invention can further reduce the cost of the circuit.

The invention belongs to the field of integrated circuits and in particular relates to a method and a device for automatically adjusting the clock frequency or the power supply voltage of a processor system in real time. The method realizes automatic and real-time adjustment of the clock frequency or the power supply voltage of the processor system by a matching step, a judging step and an adjusting step. In the running process of a processor, the clock frequency or the power supply voltage of the processor system is automatically adjusted in real time, so that the processor runs with an optimal clock frequency or an optimal power supply voltage in real time. Therefore, normal running of the system is ensured and the power consumption of the processor can be effectively lowered.

The invention provides a flip-flop circuit, and belongs to the technical field of semiconductor integrated circuits. The flip-flop circuit comprises a master latch and a secondary latch driven by clocking signals with same phases; the master latch comprises a first logic module for selectively and at least performing AND logic processing on an input data signal and the clock signal, a second logic module for at least performing NOR logic processing on the clock signal and an output signal of a third logic module, and the third logic module for selectively and at least performing the NOR logic processing on the output signal of the first logic module and the output signal of the second logic module so as to output a result to the second logic module; the secondary latch comprises a fourth logic module for at least performing the NOR logic processing on the output signal of the second logic module and the output signal of a fifth logic module, and the fifth logic module for at least performing the AND logic processing on the clock signal and an inversion signal of the output signal of the fourth logic module. The flip-flop circuit is low in dynamic power consumption.

The invention provides a storing system of an integrated video decoder, which can lower the power consumption and belongs to the decoder storing management field based on video coding and decoding standard of block. The storing system is characterized in that a compression module is used for the re-compression of reconstructed data, and the decompression is respectively carried out when reference data is read and displayed to reduce the data exchange amount of the decoder and a katanto memory; a storing address generating module is used for preparing a reasonable reference frame storing mapping structure to reduce row activation operation times required during a reading and writing process; a storing controller based on four storing signal ports structure is used for reducing the on-chip memory of the decoder and improving the bandwidth of the memory; the low power consumption coding and decoding is used for the low power consumption coding of stored contents. Static power consumption generated due to the leakage in the memory is lowered.

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

A touch sensor detector system and method incorporating an interpolated sensor array is disclosed. The system and method utilize a touch sensor array (TSA) configured to detect proximity/contact/pressure (PCP) via a variable impedance array (VIA) electrically coupling interlinked impedance columns (IIC) coupled to an array column driver (ACD), and interlinked impedance rows (IIR) coupled to an array row sensor (ARS). The ACD is configured to select the IIC based on a column switching register (CSR) and electrically drive the IIC using a column driving source (CDS). The VIA conveys current from the driven IIC to the IIC sensed by the ARS. The ARS selects the IIR within the TSA and electrically senses the IIR state based on a row switching register (RSR). Interpolation of ARS sensed current/voltage allows accurate detection of TSA PCP and/or spatial location.

Disclosed is a low power consumption static random memory with low level thread amplitude of oscillation, wherein the memory comprises a pre-charging circuit based on electric charge sharing, a memory unit, a line decoder, a row decoder, a selector, a read-write control circuit, a sensitive amplifier and an input processing circuit, wherein the bit line end of the pre-charging circuit is connected to the bidirectional port of the selector, the output end of the input treatment circuit is connected with the input end of the sensitive amplifier and the selector.